Commit d2064d4a authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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RISC-V: KVM: Sort ISA extensions alphabetically in ONE_REG interface 



Let us sort isa extensions alphabetically in kvm_isa_ext_arr[] and
kvm_riscv_vcpu_isa_disable_allowed() so that future insertions are
more predictable.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 043cba06

arch/riscv/kvm/vcpu_onereg.c

+7 −6
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 


/* Mapping between KVM ISA Extension ID & Host ISA extension ID */

static const unsigned long kvm_isa_ext_arr[] = {

	/* Single letter extensions (alphabetically sorted) */

	[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,

	[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,

	[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
@@ -32,7 +33,7 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,

	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,

	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,



	/* Multi letter extensions (alphabetically sorted) */

	KVM_ISA_EXT_ARR(SSAIA),

	KVM_ISA_EXT_ARR(SSTC),

	KVM_ISA_EXT_ARR(SVINVAL),
@@ -41,13 +42,13 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(ZBA),

	KVM_ISA_EXT_ARR(ZBB),

	KVM_ISA_EXT_ARR(ZBS),

	KVM_ISA_EXT_ARR(ZICBOM),

	KVM_ISA_EXT_ARR(ZICBOZ),

	KVM_ISA_EXT_ARR(ZICNTR),

	KVM_ISA_EXT_ARR(ZICSR),

	KVM_ISA_EXT_ARR(ZIFENCEI),

	KVM_ISA_EXT_ARR(ZIHINTPAUSE),

	KVM_ISA_EXT_ARR(ZIHPM),

	KVM_ISA_EXT_ARR(ZICBOM),

	KVM_ISA_EXT_ARR(ZICBOZ),

};



static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -87,14 +88,14 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_SSTC:

	case KVM_RISCV_ISA_EXT_SVINVAL:

	case KVM_RISCV_ISA_EXT_SVNAPOT:

	case KVM_RISCV_ISA_EXT_ZBA:

	case KVM_RISCV_ISA_EXT_ZBB:

	case KVM_RISCV_ISA_EXT_ZBS:

	case KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:

	case KVM_RISCV_ISA_EXT_ZIHPM:

	case KVM_RISCV_ISA_EXT_ZBA:

	case KVM_RISCV_ISA_EXT_ZBB:

	case KVM_RISCV_ISA_EXT_ZBS:

		return false;

	default:

		break;