Commit 043cba06 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

RISC-V: KVM: Allow Zicntr, Zicsr, Zifencei, and Zihpm for Guest/VM 



We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zicntr, Zicsr, Zifencei, and Zihpm
extensions for Guest/VM.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 41716861

arch/riscv/include/uapi/asm/kvm.h

+4 −0
Original line number Diff line number Diff line
@@ -126,6 +126,10 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_SVNAPOT,

	KVM_RISCV_ISA_EXT_ZBA,

	KVM_RISCV_ISA_EXT_ZBS,

	KVM_RISCV_ISA_EXT_ZICNTR,

	KVM_RISCV_ISA_EXT_ZICSR,

	KVM_RISCV_ISA_EXT_ZIFENCEI,

	KVM_RISCV_ISA_EXT_ZIHPM,

	KVM_RISCV_ISA_EXT_MAX,

};

arch/riscv/kvm/vcpu_onereg.c

+8 −0
Original line number Diff line number Diff line
@@ -41,7 +41,11 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(ZBA),

	KVM_ISA_EXT_ARR(ZBB),

	KVM_ISA_EXT_ARR(ZBS),

	KVM_ISA_EXT_ARR(ZICNTR),

	KVM_ISA_EXT_ARR(ZICSR),

	KVM_ISA_EXT_ARR(ZIFENCEI),

	KVM_ISA_EXT_ARR(ZIHINTPAUSE),

	KVM_ISA_EXT_ARR(ZIHPM),

	KVM_ISA_EXT_ARR(ZICBOM),

	KVM_ISA_EXT_ARR(ZICBOZ),

};
@@ -83,7 +87,11 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_SSTC:

	case KVM_RISCV_ISA_EXT_SVINVAL:

	case KVM_RISCV_ISA_EXT_SVNAPOT:

	case KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:

	case KVM_RISCV_ISA_EXT_ZIHPM:

	case KVM_RISCV_ISA_EXT_ZBA:

	case KVM_RISCV_ISA_EXT_ZBB:

	case KVM_RISCV_ISA_EXT_ZBS: