Commit d205a800 authored by Leo (Hanghong) Ma's avatar Leo (Hanghong) Ma Committed by Alex Deucher
Browse files

drm/amd/display: Add visual confirm color support for MCLK switch 



[Why && How]
We would like to have visual confirm color support for MCLK switch.
	1. Set visual confirm color to yellow: Vblank MCLK switch.
	2. Set visual confirm color to cyan: FPO + Vblank MCLK
	switch.
	3. Set visual confirm color to pink: Vactive MCLK switch.

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarLeo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1a4bcdbe

drivers/gpu/drm/amd/display/dc/core/dc.c

+42 −5
Original line number Diff line number Diff line
@@ -1119,6 +1119,33 @@ static void phantom_pipe_blank( 
		hws->funcs.wait_for_blank_complete(opp);

}



static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

{

	if (dc->ctx->dce_version >= DCN_VERSION_1_0) {

		memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));



		if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

			get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

		else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

			get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

		else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)

			get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

		else {

			if (dc->ctx->dce_version < DCN_VERSION_2_0)

				color_space_to_black_color(

					dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

		}

		if (dc->ctx->dce_version >= DCN_VERSION_2_0) {

			if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)

				get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

			else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)

				get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

			else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)

				get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

		}

	}

}



static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

{

	int i, j;
@@ -1189,6 +1216,9 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 
			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);

			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);



			if (pipe->stream && pipe->plane_state)

				dc_update_viusal_confirm_color(dc, context, pipe);



			if (dc->hwss.apply_ctx_for_surface) {

				apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);

				dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
@@ -3456,6 +3486,14 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



	if (dc->debug.visual_confirm)

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



			if (pipe->stream && pipe->plane_state)

				dc_update_viusal_confirm_color(dc, context, pipe);

		}



	if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {

		struct pipe_ctx *mpcc_pipe;

		struct pipe_ctx *odm_pipe;
@@ -3539,15 +3577,14 @@ static void commit_planes_for_stream(struct dc *dc, 
		for (j = 0; j < dc->res_pool->pipe_count; j++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];



			if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP &&

			if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||

				dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&

				pipe_ctx->stream && pipe_ctx->plane_state) {

				/* Only update visual confirm for SUBVP here.

				/* Only update visual confirm for SUBVP and Mclk switching here.

				 * The bar appears on all pipes, so we need to update the bar on all displays,

				 * so the information doesn't get stale.

				 */

				struct mpcc_blnd_cfg blnd_cfg = { 0 };



				dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color,

				dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

						pipe_ctx->plane_res.hubp->inst);

			}

		}

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

+46 −4
Original line number Diff line number Diff line
@@ -421,6 +421,7 @@ void get_hdr_visual_confirm_color( 


void get_subvp_visual_confirm_color(

		struct dc *dc,

		struct dc_state *context,

		struct pipe_ctx *pipe_ctx,

		struct tg_color *color)

{
@@ -428,15 +429,17 @@ void get_subvp_visual_confirm_color( 
	bool enable_subvp = false;

	int i;



	if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx)

	if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context)

		return;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&

		    pipe->stream->mall_stream_config.type == SUBVP_MAIN) {

			/* SubVP enable - red */

			color->color_g_y = 0;

			color->color_b_cb = 0;

			color->color_r_cr = color_value;

			enable_subvp = true;
@@ -448,13 +451,52 @@ void get_subvp_visual_confirm_color( 


	if (enable_subvp && pipe_ctx->stream->mall_stream_config.type == SUBVP_NONE) {

		color->color_r_cr = 0;

		if (pipe_ctx->stream->ignore_msa_timing_param == 1)

		if (pipe_ctx->stream->allow_freesync == 1) {

			/* SubVP enable and DRR on - green */

			color->color_b_cb = 0;

			color->color_g_y = color_value;

		else

		} else {

			/* SubVP enable and No DRR - blue */

			color->color_g_y = 0;

			color->color_b_cb = color_value;

		}

	}

}



void get_mclk_switch_visual_confirm_color(

		struct dc *dc,

		struct dc_state *context,

		struct pipe_ctx *pipe_ctx,

		struct tg_color *color)

{

	uint32_t color_value = MAX_TG_COLOR_VALUE;

	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;



	if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba || !context)

		return;



	if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=

			dm_dram_clock_change_unsupported) {

		/* MCLK switching is supported */

		if (!pipe_ctx->has_vactive_margin) {

			/* In Vblank - yellow */

			color->color_r_cr = color_value;

			color->color_g_y = color_value;



			if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

				/* FPO + Vblank - cyan */

				color->color_r_cr = 0;

				color->color_g_y  = color_value;

				color->color_b_cb = color_value;

			}

		} else {

			/* In Vactive - pink */

			color->color_r_cr = color_value;

			color->color_b_cb = color_value;

		}

		/* SubVP */

		get_subvp_visual_confirm_color(dc, context, pipe_ctx, color);

	}

}



void get_surface_tile_visual_confirm_color(

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -426,6 +426,7 @@ enum visual_confirm { 
	VISUAL_CONFIRM_FAMS = 7,

	VISUAL_CONFIRM_SWIZZLE = 9,

	VISUAL_CONFIRM_SUBVP = 14,

	VISUAL_CONFIRM_MCLK_SWITCH = 16,

};



enum dc_psr_power_opts {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+7 −15
Original line number Diff line number Diff line
@@ -2602,23 +2602,15 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state 
		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

}



void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)

void dcn10_update_visual_confirm_color(struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		int mpcc_id)

{

	struct mpc *mpc = dc->res_pool->mpc;



	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

		get_hdr_visual_confirm_color(pipe_ctx, color);

	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

		get_surface_visual_confirm_color(pipe_ctx, color);

	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)

		get_surface_tile_visual_confirm_color(pipe_ctx, color);

	else

		color_space_to_black_color(

				dc, pipe_ctx->stream->output_color_space, color);



	if (mpc->funcs->set_bg_color) {

		memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));

		mpc->funcs->set_bg_color(mpc, color, mpcc_id);

		memcpy(&pipe_ctx->plane_state->visual_confirm_color, &(pipe_ctx->visual_confirm_color), sizeof(struct tg_color));

		mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

	}

}
@@ -2671,7 +2663,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	/* If there is no full update, don't need to touch MPC tree*/

	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);

		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

		return;

	}
@@ -2693,7 +2685,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
			NULL,

			hubp->inst,

			mpcc_id);

	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);

	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);



	ASSERT(new_mpcc != NULL);

	hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+0 −1
Original line number Diff line number Diff line
@@ -202,7 +202,6 @@ void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits); 
void dcn10_update_visual_confirm_color(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		struct tg_color *color,

		int mpcc_id);



#endif /* __DC_HWSS_DCN10_H__ */