Commit 1a4bcdbe authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: Fix possible underflow for displays with large vblank 



[Why]
Underflow observed when using a display with a large vblank region
and low refresh rate

[How]
Simplify calculation of vblank_nom

Increase value for VBlankNomDefaultUS to 800us

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9c384ee8

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

+7 −12
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#include "dml/display_mode_vba.h"



struct _vcs_dpi_ip_params_st dcn3_14_ip = {

	.VBlankNomDefaultUS = 668,

	.VBlankNomDefaultUS = 800,

	.gpuvm_enable = 1,

	.gpuvm_max_page_table_levels = 1,

	.hostvm_enable = 1,
@@ -286,7 +286,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c 
	struct resource_context *res_ctx = &context->res_ctx;

	struct pipe_ctx *pipe;

	bool upscaled = false;

	bool isFreesyncVideo = false;

	const unsigned int max_allowed_vblank_nom = 1023;



	dc_assert_fp_enabled();
@@ -300,16 +300,11 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c 
		pipe = &res_ctx->pipe_ctx[i];

		timing = &pipe->stream->timing;



		isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min;

		isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total;



		if (!isFreesyncVideo) {

			pipes[pipe_cnt].pipe.dest.vblank_nom =

				dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0));

		} else {

		pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;

		pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

		}

		pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS);

		pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width);

		pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);



		if (pipe->plane_state &&

				(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||