Commit d1e2d6b7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2022-08-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



drm/i915 feature pull for v6.1:

Features and functionality:
- Early Meteorlake (MTL) enabling (José, Radhakrishna, Clint, Imre, Vandita, Ville, Jani)
- Support more HDMI pixel clock frequencies on DG2 (Clint)
- Sanity check PCI BARs (Piotr Piórkowski)
- Enable DC5 on DG2 (Anusha)
- DG2 DMC firmware version bump to v2.07 (Madhumitha)
- New ADL-S PCI ID (José)

Refactoring and cleanups:
- Add display sub-struct to struct drm_i915_private (Jani)
- Add initial runtime info to device info (Jani)
- Split out HDCP and backlight registers to separate files (Jani)

Fixes:
- Skip wm/ddb readout for disabled pipes (Ville)
- HDMI port timing quirk for GLK ECS Liva Q2 (Diego Santa Cruz)
- Fix bw init null pointer dereference (Łukasz Bartosik)
- Disable PPS power hook for DP AUX backlight (Jouni)
- Avoid warnings on registering multiple backlight devices (Arun)
- Fix dual-link DSI backlight and CABC ports for display 11+ (Jani)
- Fix Type-C PHY ownership programming in HDMI legacy mode (Imre)
- Fix unclaimed register access while loading PIPEDMC-C/D (Imre)
- Bump up CDCLK for DG2 (Stan)
- Prune modes that require HDMI 2.1 FRL (Ankit)
- Disable FBC when PSR1 is enabled in display 12-13 (Matt)
- Fix TGL+ HDMI transcoder clock and DDI BUF disable order (Imre)
- Disable PSR before disable pipe (José)
- Disable DMC handlers during firmware loading/disabling on display 12+ (Imre)
- Disable clock gating for PIPEDMC-A/B as a workaround (Imre)

Merges:
- Two drm-next backmerges (Rodrigo, Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87k06rfaku.fsf@intel.com
parents 213cb76d 917bda9a

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -1169,7 +1169,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, 
static bool ibx_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];

	u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];



	return intel_de_read(dev_priv, SDEISR) & bit;

}
@@ -1223,7 +1223,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder) 
static bool ilk_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];

	u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];



	return intel_de_read(dev_priv, DEISR) & bit;

}

drivers/gpu/drm/i915/display/icl_dsi.c

+12 −8
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "icl_dsi_regs.h"

#include "intel_atomic.h"

#include "intel_backlight.h"

#include "intel_backlight_regs.h"

#include "intel_combo_phy.h"

#include "intel_combo_phy_regs.h"

#include "intel_connector.h"
@@ -641,13 +642,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 
	u32 tmp;

	enum phy phy;



	mutex_lock(&dev_priv->dpll.lock);

	mutex_lock(&dev_priv->display.dpll.lock);

	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);

	for_each_dsi_phy(phy, intel_dsi->phys)

		tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);



	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);

	mutex_unlock(&dev_priv->dpll.lock);

	mutex_unlock(&dev_priv->display.dpll.lock);

}



static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
@@ -657,13 +658,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 
	u32 tmp;

	enum phy phy;



	mutex_lock(&dev_priv->dpll.lock);

	mutex_lock(&dev_priv->display.dpll.lock);

	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);

	for_each_dsi_phy(phy, intel_dsi->phys)

		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);



	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);

	mutex_unlock(&dev_priv->dpll.lock);

	mutex_unlock(&dev_priv->display.dpll.lock);

}



static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
@@ -693,7 +694,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, 
	enum phy phy;

	u32 val;



	mutex_lock(&dev_priv->dpll.lock);

	mutex_lock(&dev_priv->display.dpll.lock);



	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);

	for_each_dsi_phy(phy, intel_dsi->phys) {
@@ -709,7 +710,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, 


	intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);



	mutex_unlock(&dev_priv->dpll.lock);

	mutex_unlock(&dev_priv->display.dpll.lock);

}



static void
@@ -2070,8 +2071,11 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	else

		intel_dsi->ports = BIT(port);



	intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;

	intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;

	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))

		intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;



	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))

		intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;



	for_each_dsi_port(port, intel_dsi->ports) {

		struct intel_dsi_host *host;

drivers/gpu/drm/i915/display/intel_audio.c

+48 −48
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, 
			   const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct i915_audio_component *acomp = dev_priv->audio.component;

	struct i915_audio_component *acomp = dev_priv->display.audio.component;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	enum port port = encoder->port;

	const struct dp_aud_n_m *nm;
@@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 
			     const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct i915_audio_component *acomp = dev_priv->audio.component;

	struct i915_audio_component *acomp = dev_priv->display.audio.component;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	enum port port = encoder->port;

	int n, rate;
@@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, 
	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;

	u32 tmp;



	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);



	/* Disable timestamps */

	tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
@@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, 
	tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);

	intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);



	mutex_unlock(&dev_priv->audio.mutex);

	mutex_unlock(&dev_priv->display.audio.mutex);

}



static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
@@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, 
	u32 tmp;

	int len, i;



	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);



	/* Enable Audio WA for 4k DSC usecases */

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
@@ -677,7 +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, 
	/* Enable timestamps */

	hsw_audio_config_update(encoder, crtc_state);



	mutex_unlock(&dev_priv->audio.mutex);

	mutex_unlock(&dev_priv->display.audio.mutex);

}



static void ilk_audio_codec_disable(struct intel_encoder *encoder,
@@ -814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, 
			      const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct i915_audio_component *acomp = dev_priv->audio.component;

	struct i915_audio_component *acomp = dev_priv->display.audio.component;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_connector *connector = conn_state->connector;

	const struct drm_display_mode *adjusted_mode =
@@ -838,17 +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, 


	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;



	if (dev_priv->audio.funcs)

		dev_priv->audio.funcs->audio_codec_enable(encoder,

	if (dev_priv->display.funcs.audio)

		dev_priv->display.funcs.audio->audio_codec_enable(encoder,

								  crtc_state,

								  conn_state);



	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);

	encoder->audio_connector = connector;



	/* referred in audio callbacks */

	dev_priv->audio.encoder_map[pipe] = encoder;

	mutex_unlock(&dev_priv->audio.mutex);

	dev_priv->display.audio.encoder_map[pipe] = encoder;

	mutex_unlock(&dev_priv->display.audio.mutex);



	if (acomp && acomp->base.audio_ops &&

	    acomp->base.audio_ops->pin_eld_notify) {
@@ -878,7 +878,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, 
			       const struct drm_connector_state *old_conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct i915_audio_component *acomp = dev_priv->audio.component;

	struct i915_audio_component *acomp = dev_priv->display.audio.component;

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	struct drm_connector *connector = old_conn_state->connector;

	enum port port = encoder->port;
@@ -891,15 +891,15 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, 
		    connector->base.id, connector->name,

		    encoder->base.base.id, encoder->base.name, pipe_name(pipe));



	if (dev_priv->audio.funcs)

		dev_priv->audio.funcs->audio_codec_disable(encoder,

	if (dev_priv->display.funcs.audio)

		dev_priv->display.funcs.audio->audio_codec_disable(encoder,

								   old_crtc_state,

								   old_conn_state);



	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);

	encoder->audio_connector = NULL;

	dev_priv->audio.encoder_map[pipe] = NULL;

	mutex_unlock(&dev_priv->audio.mutex);

	dev_priv->display.audio.encoder_map[pipe] = NULL;

	mutex_unlock(&dev_priv->display.audio.mutex);



	if (acomp && acomp->base.audio_ops &&

	    acomp->base.audio_ops->pin_eld_notify) {
@@ -935,13 +935,13 @@ static const struct intel_audio_funcs hsw_audio_funcs = { 
void intel_audio_hooks_init(struct drm_i915_private *dev_priv)

{

	if (IS_G4X(dev_priv)) {

		dev_priv->audio.funcs = &g4x_audio_funcs;

		dev_priv->display.funcs.audio = &g4x_audio_funcs;

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		dev_priv->audio.funcs = &ilk_audio_funcs;

		dev_priv->display.funcs.audio = &ilk_audio_funcs;

	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {

		dev_priv->audio.funcs = &hsw_audio_funcs;

		dev_priv->display.funcs.audio = &hsw_audio_funcs;

	} else if (HAS_PCH_SPLIT(dev_priv)) {

		dev_priv->audio.funcs = &ilk_audio_funcs;

		dev_priv->display.funcs.audio = &ilk_audio_funcs;

	}

}
@@ -1046,13 +1046,13 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 


	ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);



	if (dev_priv->audio.power_refcount++ == 0) {

	if (dev_priv->display.audio.power_refcount++ == 0) {

		if (DISPLAY_VER(dev_priv) >= 9) {

			intel_de_write(dev_priv, AUD_FREQ_CNTRL,

				       dev_priv->audio.freq_cntrl);

				       dev_priv->display.audio.freq_cntrl);

			drm_dbg_kms(&dev_priv->drm,

				    "restored AUD_FREQ_CNTRL to 0x%x\n",

				    dev_priv->audio.freq_cntrl);

				    dev_priv->display.audio.freq_cntrl);

		}



		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
@@ -1073,7 +1073,7 @@ static void i915_audio_component_put_power(struct device *kdev, 
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);



	/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */

	if (--dev_priv->audio.power_refcount == 0)

	if (--dev_priv->display.audio.power_refcount == 0)

		if (IS_GEMINILAKE(dev_priv))

			glk_force_audio_cdclk(dev_priv, false);
@@ -1140,10 +1140,10 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 
	/* MST */

	if (pipe >= 0) {

		if (drm_WARN_ON(&dev_priv->drm,

				pipe >= ARRAY_SIZE(dev_priv->audio.encoder_map)))

				pipe >= ARRAY_SIZE(dev_priv->display.audio.encoder_map)))

			return NULL;



		encoder = dev_priv->audio.encoder_map[pipe];

		encoder = dev_priv->display.audio.encoder_map[pipe];

		/*

		 * when bootup, audio driver may not know it is

		 * MST or not. So it will poll all the port & pipe
@@ -1159,7 +1159,7 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 
		return NULL;



	for_each_pipe(dev_priv, pipe) {

		encoder = dev_priv->audio.encoder_map[pipe];

		encoder = dev_priv->display.audio.encoder_map[pipe];

		if (encoder == NULL)

			continue;
@@ -1177,7 +1177,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 
						int pipe, int rate)

{

	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);

	struct i915_audio_component *acomp = dev_priv->audio.component;

	struct i915_audio_component *acomp = dev_priv->display.audio.component;

	struct intel_encoder *encoder;

	struct intel_crtc *crtc;

	unsigned long cookie;
@@ -1187,7 +1187,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 
		return 0;



	cookie = i915_audio_component_get_power(kdev);

	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);



	/* 1. get the pipe */

	encoder = get_saved_enc(dev_priv, port, pipe);
@@ -1206,7 +1206,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 
	hsw_audio_config_update(encoder, crtc->config);



 unlock:

	mutex_unlock(&dev_priv->audio.mutex);

	mutex_unlock(&dev_priv->display.audio.mutex);

	i915_audio_component_put_power(kdev, cookie);

	return err;

}
@@ -1220,13 +1220,13 @@ static int i915_audio_component_get_eld(struct device *kdev, int port, 
	const u8 *eld;

	int ret = -EINVAL;



	mutex_lock(&dev_priv->audio.mutex);

	mutex_lock(&dev_priv->display.audio.mutex);



	intel_encoder = get_saved_enc(dev_priv, port, pipe);

	if (!intel_encoder) {

		drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",

			    port_name(port));

		mutex_unlock(&dev_priv->audio.mutex);

		mutex_unlock(&dev_priv->display.audio.mutex);

		return ret;

	}
@@ -1238,7 +1238,7 @@ static int i915_audio_component_get_eld(struct device *kdev, int port, 
		memcpy(buf, eld, min(max_bytes, ret));

	}



	mutex_unlock(&dev_priv->audio.mutex);

	mutex_unlock(&dev_priv->display.audio.mutex);

	return ret;

}
@@ -1273,7 +1273,7 @@ static int i915_audio_component_bind(struct device *i915_kdev, 
	BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);

	for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)

		acomp->aud_sample_rate[i] = 0;

	dev_priv->audio.component = acomp;

	dev_priv->display.audio.component = acomp;

	drm_modeset_unlock_all(&dev_priv->drm);



	return 0;
@@ -1288,14 +1288,14 @@ static void i915_audio_component_unbind(struct device *i915_kdev, 
	drm_modeset_lock_all(&dev_priv->drm);

	acomp->base.ops = NULL;

	acomp->base.dev = NULL;

	dev_priv->audio.component = NULL;

	dev_priv->display.audio.component = NULL;

	drm_modeset_unlock_all(&dev_priv->drm);



	device_link_remove(hda_kdev, i915_kdev);



	if (dev_priv->audio.power_refcount)

	if (dev_priv->display.audio.power_refcount)

		drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",

			dev_priv->audio.power_refcount);

			dev_priv->display.audio.power_refcount);

}



static const struct component_ops i915_audio_component_bind_ops = {
@@ -1359,13 +1359,13 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) 
		drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",

			    aud_freq, aud_freq_init);



		dev_priv->audio.freq_cntrl = aud_freq;

		dev_priv->display.audio.freq_cntrl = aud_freq;

	}



	/* init with current cdclk */

	intel_audio_cdclk_change_post(dev_priv);



	dev_priv->audio.component_registered = true;

	dev_priv->display.audio.component_registered = true;

}



/**
@@ -1377,11 +1377,11 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) 
 */

static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)

{

	if (!dev_priv->audio.component_registered)

	if (!dev_priv->display.audio.component_registered)

		return;



	component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);

	dev_priv->audio.component_registered = false;

	dev_priv->display.audio.component_registered = false;

}



/**
@@ -1403,7 +1403,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv) 
 */

void intel_audio_deinit(struct drm_i915_private *dev_priv)

{

	if ((dev_priv)->audio.lpe.platdev != NULL)

	if (dev_priv->display.audio.lpe.platdev != NULL)

		intel_lpe_audio_teardown(dev_priv);

	else

		i915_audio_component_cleanup(dev_priv);

drivers/gpu/drm/i915/display/intel_backlight.c

+21 −17
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/string_helpers.h>



#include "intel_backlight.h"

#include "intel_backlight_regs.h"

#include "intel_connector.h"

#include "intel_de.h"

#include "intel_display_types.h"
@@ -16,6 +17,7 @@ 
#include "intel_dsi_dcs_backlight.h"

#include "intel_panel.h"

#include "intel_pci_config.h"

#include "intel_pps.h"



/**

 * scale - scale values from one range to another
@@ -971,9 +973,9 @@ int intel_backlight_device_register(struct intel_connector *connector) 
	if (!name)

		return -ENOMEM;



	bd = backlight_device_register(name, connector->base.kdev, connector,

				       &intel_backlight_device_ops, &props);



	bd = backlight_device_get_by_name(name);

	if (bd) {

		put_device(&bd->dev);

		/*

		 * Using the same name independent of the drm device or connector

		 * prevents registration of multiple backlight devices in the
@@ -981,16 +983,14 @@ int intel_backlight_device_register(struct intel_connector *connector) 
		 * compatibility. Use unique names for subsequent backlight devices as a

		 * fallback when the default name already exists.

		 */

	if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {

		kfree(name);

		name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",

				 i915->drm.primary->index, connector->base.name);

		if (!name)

			return -ENOMEM;



	}

	bd = backlight_device_register(name, connector->base.kdev, connector,

				       &intel_backlight_device_ops, &props);

	}



	if (IS_ERR(bd)) {

		drm_err(&i915->drm,
@@ -1773,10 +1773,14 @@ void intel_backlight_init_funcs(struct intel_panel *panel) 
		panel->backlight.pwm_funcs = &i9xx_pwm_funcs;

	}



	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&

	    intel_dp_aux_init_backlight_funcs(connector) == 0)

	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {

		if (intel_dp_aux_init_backlight_funcs(connector) == 0)

			return;



		if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))

			connector->panel.backlight.power = intel_pps_backlight_power;

	}



	/* We're using a standard PWM backlight interface */

	panel->backlight.funcs = &pwm_bl_funcs;

}

drivers/gpu/drm/i915/display/intel_backlight_regs.h

0 → 100644
+124 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2022 Intel Corporation

 */



#ifndef __INTEL_BACKLIGHT_REGS_H__

#define __INTEL_BACKLIGHT_REGS_H__



#include "i915_reg_defs.h"



#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)

#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)

#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \

					 _VLV_BLC_PWM_CTL2_B)



#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)

#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)

#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \

					_VLV_BLC_PWM_CTL_B)



#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)

#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)

#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \

					 _VLV_BLC_HIST_CTL_B)



/* Backlight control */

#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */

#define   BLM_PWM_ENABLE		(1 << 31)

#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */

#define   BLM_PIPE_SELECT		(1 << 29)

#define   BLM_PIPE_SELECT_IVB		(3 << 29)

#define   BLM_PIPE_A			(0 << 29)

#define   BLM_PIPE_B			(1 << 29)

#define   BLM_PIPE_C			(2 << 29) /* ivb + */

#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */

#define   BLM_TRANSCODER_B		BLM_PIPE_B

#define   BLM_TRANSCODER_C		BLM_PIPE_C

#define   BLM_TRANSCODER_EDP		(3 << 29)

#define   BLM_PIPE(pipe)		((pipe) << 29)

#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */

#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)

#define   BLM_PHASE_IN_ENABLE		(1 << 25)

#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)

#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)

#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)

#define   BLM_PHASE_IN_COUNT_SHIFT	(8)

#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)

#define   BLM_PHASE_IN_INCR_SHIFT	(0)

#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)

#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)

/*

 * This is the most significant 15 bits of the number of backlight cycles in a

 * complete cycle of the modulated backlight control.

 *

 * The actual value is this field multiplied by two.

 */

#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)

#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)

#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */

/*

 * This is the number of cycles out of the backlight modulation cycle for which

 * the backlight is on.

 *

 * This field must be no greater than the number of cycles in the complete

 * backlight modulation cycle.

 */

#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)

#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)

#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)

#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */



#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)

#define  BLM_HISTOGRAM_ENABLE			(1 << 31)



/* New registers for PCH-split platforms. Safe where new bits show up, the

 * register layout machtes with gen4 BLC_PWM_CTL[12]. */

#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)

#define BLC_PWM_CPU_CTL		_MMIO(0x48254)



#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)



/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is

 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */

#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)

#define   BLM_PCH_PWM_ENABLE			(1 << 31)

#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)

#define   BLM_PCH_POLARITY			(1 << 29)

#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)



/* BXT backlight register definition. */

#define _BXT_BLC_PWM_CTL1			0xC8250

#define   BXT_BLC_PWM_ENABLE			(1 << 31)

#define   BXT_BLC_PWM_POLARITY			(1 << 29)

#define _BXT_BLC_PWM_FREQ1			0xC8254

#define _BXT_BLC_PWM_DUTY1			0xC8258



#define _BXT_BLC_PWM_CTL2			0xC8350

#define _BXT_BLC_PWM_FREQ2			0xC8354

#define _BXT_BLC_PWM_DUTY2			0xC8358



#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\

					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)

#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \

					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)

#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \

					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)



/* Utility pin */

#define UTIL_PIN_CTL			_MMIO(0x48400)

#define   UTIL_PIN_ENABLE		(1 << 31)

#define   UTIL_PIN_PIPE_MASK		(3 << 29)

#define   UTIL_PIN_PIPE(x)		((x) << 29)

#define   UTIL_PIN_MODE_MASK		(0xf << 24)

#define   UTIL_PIN_MODE_DATA		(0 << 24)

#define   UTIL_PIN_MODE_PWM		(1 << 24)

#define   UTIL_PIN_MODE_VBLANK		(4 << 24)

#define   UTIL_PIN_MODE_VSYNC		(5 << 24)

#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)

#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)

#define   UTIL_PIN_POLARITY		(1 << 22)

#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)

#define   UTIL_PIN_INPUT_DATA		(1 << 16)



#endif /* __INTEL_BACKLIGHT_REGS_H__ */