x86/fpu/xstate: Prepare XSAVE feature table for gaps in state component numbers

mainline inclusion
from mainline-v5.16-rc1
commit 70c3f167
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I590ZC


CVE: NA

Intel-SIG: commit 70c3f167 x86/fpu/xstate: Prepare XSAVE feature table for gaps in state component numbers.

--------------------------------

The kernel checks at boot time which features are available by walking a
XSAVE feature table which contains the CPUID feature bit numbers which need
to be checked whether a feature is available on a CPU or not. So far the
feature numbers have been linear, but AMX will create a gap which the
current code cannot handle.

Make the table entries explicitly indexed and adjust the loop code
accordingly to prepare for that.

No functional change.

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20211021225527.10184-20-chang.seok.bae@intel.com


Signed-off-by: Lin Wang <lin.x.wang@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>