Commit d16d30f4 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools headers cpufeatures: Sync with the kernel sources 

To pick the changes from:

  fa31a4d6 ("x86/cpufeatures: Put the AMX macros in the word 18 block")
  7b8f40b3 ("x86/cpu: Add definitions for the Intel Hardware Feedback Interface")

This only causes these perf files to be rebuilt:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Borislav Petkov <bp@suse.de>
Cc: Jim Mattson <jmattson@google.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Link: https://lore.kernel.org/lkml/YjzZPxdyLjf76gM+@kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 1efe4cbd

tools/arch/x86/include/asm/cpufeatures.h

+4 −3
Original line number Diff line number Diff line
@@ -299,9 +299,6 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -330,6 +327,7 @@ 
#define X86_FEATURE_HWP_ACT_WINDOW	(14*32+ 9) /* HWP Activity Window */

#define X86_FEATURE_HWP_EPP		(14*32+10) /* HWP Energy Perf. Preference */

#define X86_FEATURE_HWP_PKG_REQ		(14*32+11) /* HWP Package Level Request */

#define X86_FEATURE_HFI			(14*32+19) /* Hardware Feedback Interface */



/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */

#define X86_FEATURE_NPT			(15*32+ 0) /* Nested Page Table support */
@@ -390,7 +388,10 @@ 
#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */