Commit fa31a4d6 authored by Jim Mattson's avatar Jim Mattson Committed by Borislav Petkov
Browse files

x86/cpufeatures: Put the AMX macros in the word 18 block 



These macros are for bits in CPUID.(EAX=7,ECX=0):EDX, not for bits in
CPUID(EAX=7,ECX=1):EAX. Put them with their brethren.

  [ bp: Sort word 18 bits properly, as caught by Like Xu
    <like.xu.linux@gmail.com> ]

Signed-off-by: default avatarJim Mattson <jmattson@google.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20220203194308.2469117-1-jmattson@google.com
parent ab28e944

arch/x86/include/asm/cpufeatures.h

+3 −3
Original line number Diff line number Diff line
@@ -299,9 +299,6 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -390,7 +387,10 @@ 
#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */