perf/x86/intel/uncore: Support IMC free-running counters on Sapphire Rapids server

mainline inclusion
from mainline-v5.15-rc1
commit c76826a6
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit c76826a6 perf/x86/intel/uncore: Support IMC
free-running counters on Sapphire Rapids server
This commit is backported for SPR PMU uncore support.

-------------------------------------

Several free-running counters for IMC uncore blocks are supported on
Sapphire Rapids server.

They are not enumerated in the discovery tables. The number of the
free-running counter boxes is calculated from the number of
corresponding standard boxes.

The snbep_pci2phy_map_init() is invoked to setup the mapping from a PCI
BUS to a Die ID, which is used to locate the corresponding MC device of
a IMC uncore unit in the spr_uncore_imc_freerunning_init_box().

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-16-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>