Commit d135368d authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Extract hsw_ddi_{enable,disable}_clock() 



Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.

v2: s/dev_priv/i915/ (Lucas)
v3: Deal with FDI

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> #v2
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-4-ville.syrjala@linux.intel.com
parent c133df69

drivers/gpu/drm/i915/display/intel_crt.c

+2 −0
Original line number Diff line number Diff line
@@ -1076,6 +1076,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) 
		crt->base.enable = hsw_enable_crt;

		crt->base.disable = hsw_disable_crt;

		crt->base.post_disable = hsw_post_disable_crt;

		crt->base.enable_clock = hsw_ddi_enable_clock;

		crt->base.disable_clock = hsw_ddi_disable_clock;

	} else {

		if (HAS_PCH_SPLIT(dev_priv)) {

			crt->base.compute_config = pch_crt_compute_config;

drivers/gpu/drm/i915/display/intel_ddi.c

+26 −6
Original line number Diff line number Diff line
@@ -1898,9 +1898,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, 


		intel_de_write(dev_priv, DPLL_CTRL2, val);



	} else if (INTEL_GEN(dev_priv) < 9) {

		intel_de_write(dev_priv, PORT_CLK_SEL(port),

			       hsw_pll_to_ddi_pll_sel(pll));

	}



	mutex_unlock(&dev_priv->dpll.lock);
@@ -1923,12 +1920,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) 
	} else if (IS_GEN9_BC(dev_priv)) {

		intel_de_write(dev_priv, DPLL_CTRL2,

			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));

	} else if (INTEL_GEN(dev_priv) < 9) {

		intel_de_write(dev_priv, PORT_CLK_SEL(port),

			       PORT_CLK_SEL_NONE);

	}

}



void hsw_ddi_enable_clock(struct intel_encoder *encoder,

			  const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	enum port port = encoder->port;



	if (drm_WARN_ON(&i915->drm, !pll))

		return;



	intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));

}



void hsw_ddi_disable_clock(struct intel_encoder *encoder)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum port port = encoder->port;



	intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);

}



void intel_ddi_enable_clock(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state)

{
@@ -4083,6 +4098,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
	encoder->cloneable = 0;

	encoder->pipe_mask = ~0;



	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {

		encoder->enable_clock = hsw_ddi_enable_clock;

		encoder->disable_clock = hsw_ddi_disable_clock;

	}



	if (IS_DG1(dev_priv))

		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);

	else if (IS_ROCKETLAKE(dev_priv))

drivers/gpu/drm/i915/display/intel_ddi.h

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 
				const struct drm_connector_state *old_conn_state);

void intel_ddi_enable_clock(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state);

void hsw_ddi_enable_clock(struct intel_encoder *encoder,

			  const struct intel_crtc_state *crtc_state);

void hsw_ddi_disable_clock(struct intel_encoder *encoder);

void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state);

void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,