Loading arch/arm/mach-mmp/Makefile +3 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o endif ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o endif # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o Loading arch/arm/mach-mmp/platsmp.c 0 → 100644 +32 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk> */ #include <linux/io.h> #include <asm/smp_scu.h> #include <asm/smp.h> #include "addr-map.h" #define SW_BRANCH_VIRT_ADDR CIU_REG(0x24) static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle) { /* * Apparently, the boot ROM on the second core spins on this * register becoming non-zero and then jumps to the address written * there. No IPIs involved. */ __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR); return 0; } static void mmp3_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(SCU_VIRT_BASE); } static const struct smp_operations mmp3_smp_ops __initconst = { .smp_prepare_cpus = mmp3_smp_prepare_cpus, .smp_boot_secondary = mmp3_boot_secondary, }; CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops); Loading
arch/arm/mach-mmp/Makefile +3 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o endif ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o endif # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o Loading
arch/arm/mach-mmp/platsmp.c 0 → 100644 +32 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk> */ #include <linux/io.h> #include <asm/smp_scu.h> #include <asm/smp.h> #include "addr-map.h" #define SW_BRANCH_VIRT_ADDR CIU_REG(0x24) static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle) { /* * Apparently, the boot ROM on the second core spins on this * register becoming non-zero and then jumps to the address written * there. No IPIs involved. */ __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR); return 0; } static void mmp3_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(SCU_VIRT_BASE); } static const struct smp_operations mmp3_smp_ops __initconst = { .smp_prepare_cpus = mmp3_smp_prepare_cpus, .smp_boot_secondary = mmp3_boot_secondary, }; CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);