Commit a9372a5f authored by Lubomir Rintel's avatar Lubomir Rintel
Browse files

ARM: mmp: add support for MMP3 SoC 



Similar to MMP2, which this patch is based on. Known differencies from MMP2
are:

* Two PJ4B cores instead of one PJ4
* Tauros 3 L2 cache controller instead of Tauros 2
* A GIC interrupt controller optionally used instead of the MMP one
* A TWD local timer
* Different USB2 PHY
* A USB3 SS controller
* More interrupt muxes

Hard to tell what else is different, because documentation is not
available.

Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
parent 199c936e

arch/arm/mach-mmp/Kconfig

+20 −2
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

menuconfig ARCH_MMP

	bool "Marvell PXA168/910/MMP2"

	bool "Marvell PXA168/910/MMP2/MMP3"

	depends on ARCH_MULTI_V5 || ARCH_MULTI_V7

	select GPIO_PXA

	select GPIOLIB

	select PINCTRL

	select PLAT_PXA

	help

	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.

	  Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.



if ARCH_MMP
@@ -129,6 +129,24 @@ config MACH_MMP2_DT 
	  Include support for Marvell MMP2 based platforms using

	  the device tree.



config MACH_MMP3_DT

	bool "Support MMP3 (ARMv7) platforms"

	depends on ARCH_MULTI_V7

	select ARM_GIC

	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_TWD if SMP

	select CACHE_L2X0

	select PINCTRL

	select PINCTRL_SINGLE

	select ARCH_HAS_RESET_CONTROLLER

	select CPU_PJ4B

	select PM_GENERIC_DOMAINS if PM

	select PM_GENERIC_DOMAINS_OF if PM && OF

	help

	  Say 'Y' here if you want to include support for platforms

	  with Marvell MMP3 processor, also known as PXA2128 or

	  Armada 620.



endmenu



config CPU_PXA168

arch/arm/mach-mmp/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -34,5 +34,6 @@ obj-$(CONFIG_MACH_FLINT) += flint.o 
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o

obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o

obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o

obj-$(CONFIG_MACH_MMP3_DT)	+= mmp3.o

obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o

obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o

arch/arm/mach-mmp/cputype.h

+27 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
 * MMP2	     Z0	   0x560f5811   0x00F00410

 * MMP2      Z1    0x560f5811   0x00E00410

 * MMP2      A0    0x560f5811   0x00A0A610

 * MMP3      A0    0x562f5842   0x00A02128

 * MMP3      B0    0x562f5842   0x00B02128

 */



extern unsigned int mmp_chip_id;
@@ -55,4 +57,29 @@ static inline int cpu_is_mmp2(void) 
#define cpu_is_mmp2()	(0)

#endif



#ifdef CONFIG_MACH_MMP3_DT

static inline int cpu_is_mmp3(void)

{

	return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&

		((mmp_chip_id & 0xffff) == 0x2128);

}



static inline int cpu_is_mmp3_a0(void)

{

	return (cpu_is_mmp3() &&

		((mmp_chip_id & 0x00ff0000) == 0x00a00000));

}



static inline int cpu_is_mmp3_b0(void)

{

	return (cpu_is_mmp3() &&

		((mmp_chip_id & 0x00ff0000) == 0x00b00000));

}



#else

#define cpu_is_mmp3()		(0)

#define cpu_is_mmp3_a0()	(0)

#define cpu_is_mmp3_b0()	(0)

#endif



#endif /* __ASM_MACH_CPUTYPE_H */

arch/arm/mach-mmp/mmp3.c

0 → 100644
+29 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 *  Marvell MMP3 aka PXA2128 aka 88AP2128 support

 *

 *  Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>

 */



#include <linux/io.h>

#include <linux/irqchip.h>

#include <linux/of_platform.h>

#include <linux/clk-provider.h>

#include <asm/mach/arch.h>

#include <asm/hardware/cache-l2x0.h>



#include "common.h"



static const char *const mmp3_dt_board_compat[] __initconst = {

	"marvell,mmp3",

	NULL,

};



DT_MACHINE_START(MMP2_DT, "Marvell MMP3")

	.map_io		= mmp2_map_io,

	.dt_compat	= mmp3_dt_board_compat,

	.l2c_aux_val	= 1 << L310_AUX_CTRL_FWA_SHIFT |

			  L310_AUX_CTRL_DATA_PREFETCH |

			  L310_AUX_CTRL_INSTR_PREFETCH,

	.l2c_aux_mask	= 0xc20fffff,

MACHINE_END

arch/arm/mach-mmp/time.c

+2 −1
Original line number Diff line number Diff line
@@ -155,7 +155,8 @@ static void __init timer_config(void) 


	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */



	ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :

	ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?

		(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :

		(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));

	__raw_writel(ccr, mmp_timer_base + TMR_CCR);