Commit d044f814 authored by Fuad Tabba's avatar Fuad Tabba Committed by Will Deacon
Browse files

arm64: Fix comments to refer to correct function __flush_icache_range 



Many comments refer to the function flush_icache_range, where the
intent is in fact __flush_icache_range. Fix these comments to
refer to the intended function.

That's probably due to commit 3b8c9f1c ("arm64: IPI each
CPU after invalidating the I-cache for kernel mappings"), which
renamed flush_icache_range() to __flush_icache_range() and added
a wrapper.

No functional change intended.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-10-tabba@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 06b7a568

arch/arm64/kernel/hibernate-asm.S

+2 −2
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
 * Because this code has to be copied to a 'safe' page, it can't call out to

 * other functions by PC-relative address. Also remember that it may be

 * mid-way through over-writing other functions. For this reason it contains

 * code from flush_icache_range() and uses the copy_page() macro.

 * code from __flush_icache_range() and uses the copy_page() macro.

 *

 * This 'safe' page is mapped via ttbr0, and executed from there. This function

 * switches to a copy of the linear map in ttbr1, performs the restore, then
@@ -87,7 +87,7 @@ SYM_CODE_START(swsusp_arch_suspend_exit) 
	copy_page	x0, x1, x2, x3, x4, x5, x6, x7, x8, x9



	add	x1, x10, #PAGE_SIZE

	/* Clean the copied page to PoU - based on flush_icache_range() */

	/* Clean the copied page to PoU - based on __flush_icache_range() */

	raw_dcache_line_size x2, x3

	sub	x3, x2, #1

	bic	x4, x10, x3

arch/arm64/mm/cache.S

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ alternative_else_nop_endif 
.endm



/*

 *	flush_icache_range(start,end)

 *	__flush_icache_range(start,end)

 *

 *	Ensure that the I and D caches are coherent within specified region.

 *	This is typically used when code has been written to a memory region,