selftests/sgx: Add test for multiple TCS entry

mainline inclusion
from mainline-5.17-rc1
commit 688542e2
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5USAM


CVE: NA

Intel-SIG: commit 688542e2 selftests/sgx: Add test for multiple TCS
entry.
Backport for SGX EDMM support.

--------------------------------

Each thread executing in an enclave is associated with a Thread Control
Structure (TCS). The SGX test enclave contains two hardcoded TCS, thus
supporting two threads in the enclave.

Add a test to ensure it is possible to enter enclave at both entrypoints.

Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lkml.kernel.org/r/7be151a57b4c7959a2364753b995e0006efa3da1.1636997631.git.reinette.chatre@intel.com


Signed-off-by: Zhiquan Li <zhiquan1.li@intel.com>