Commit cede849e authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add ATHUB IP v3.0.1 Clock Gating support 



Add ATHUB IP v3.0.1 in athub_v3_0_set_clockgating.

The regATHUB_MISC_CNTL has different offset for ATHUB IP v3.0.1,
so need to add IP version checking to use the right REG offset.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73c49a62

drivers/gpu/drm/amd/amdgpu/athub_v3_0.c

+37 −5
Original line number Diff line number Diff line
@@ -28,13 +28,44 @@ 
#include "navi10_enum.h"

#include "soc15_common.h"



#define regATHUB_MISC_CNTL_V3_0_1			0x00d7

#define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX		0





static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)

{

	uint32_t data;



	switch (adev->ip_versions[ATHUB_HWIP][0]) {

	case IP_VERSION(3, 0, 1):

		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);

		break;

	default:

		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

		break;

	}

	return data;

}



static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)

{

	switch (adev->ip_versions[ATHUB_HWIP][0]) {

	case IP_VERSION(3, 0, 1):

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);

		break;

	default:

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);

		break;

	}

}



static void

athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,

					    bool enable)

{

	uint32_t def, data;



	def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

	def = data = athub_v3_0_get_cg_cntl(adev);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))

		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
@@ -42,7 +73,7 @@ athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;



	if (def != data)

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);

		athub_v3_0_set_cg_cntl(adev, data);

}



static void
@@ -51,7 +82,7 @@ athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
{

	uint32_t def, data;



	def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

	def = data = athub_v3_0_get_cg_cntl(adev);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))

		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
@@ -59,7 +90,7 @@ athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;



	if (def != data)

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);

		athub_v3_0_set_cg_cntl(adev, data);

}



int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
@@ -70,6 +101,7 @@ int athub_v3_0_set_clockgating(struct amdgpu_device *adev, 


	switch (adev->ip_versions[ATHUB_HWIP][0]) {

	case IP_VERSION(3, 0, 0):

	case IP_VERSION(3, 0, 1):

	case IP_VERSION(3, 0, 2):

		athub_v3_0_update_medium_grain_clock_gating(adev,

				state == AMD_CG_STATE_GATE);
@@ -88,7 +120,7 @@ void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 
	int data;



	/* AMD_CG_SUPPORT_ATHUB_MGCG */

	data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

	data = athub_v3_0_get_cg_cntl(adev);

	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)

		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;