Commit 73c49a62 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add HDP IP v5.2.1 Clock Gating support 



Add set/get_clockgating for HDP IP v5.2.1.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8172ceba

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

+150 −0
Original line number Diff line number Diff line
@@ -40,6 +40,156 @@ static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev, 
			0);

}



static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,

					     bool enable)

{

	uint32_t hdp_clk_cntl;

	uint32_t hdp_mem_pwr_cntl;



	if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |

				AMD_CG_SUPPORT_HDP_DS |

				AMD_CG_SUPPORT_HDP_SD)))

		return;



	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);



	/* Before doing clock/power mode switch, forced on MEM clock */

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     ATOMIC_MEM_CLK_SOFT_OVERRIDE, 1);

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     RC_MEM_CLK_SOFT_OVERRIDE, 1);

	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);



	/* disable clock and power gating before any changing */

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_CTRL_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_LS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_DS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_SD_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_CTRL_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_LS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_DS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_SD_EN, 0);

	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);



	/* Already disabled above. The actions below are for "enabled" only */

	if (enable) {

		/* only one clock gating mode (LS/DS/SD) can be enabled */

		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_SD_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_SD_EN, 1);

		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_LS_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_LS_EN, 1);

		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_DS_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_DS_EN, 1);

		}



		/* confirmed that ATOMIC/RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD */

		if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |

				      AMD_CG_SUPPORT_HDP_SD)) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_CTRL_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_CTRL_EN, 1);

			WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);

		}

	}



	/* disable MEM clock override after clock/power mode changing */

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     ATOMIC_MEM_CLK_SOFT_OVERRIDE, 0);

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     RC_MEM_CLK_SOFT_OVERRIDE, 0);

	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);

}



static void hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,

						      bool enable)

{

	uint32_t hdp_clk_cntl;



	if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

		return;



	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);



	if (enable) {

		hdp_clk_cntl &=

			~(uint32_t)

			(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);

	} else {

		hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;

	}



	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);

}



static void hdp_v5_2_get_clockgating_state(struct amdgpu_device *adev,

					   u64 *flags)

{

	uint32_t tmp;



	/* AMD_CG_SUPPORT_HDP_MGCG */

	tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

	if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))

		*flags |= AMD_CG_SUPPORT_HDP_MGCG;



	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */

	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_LS;

	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_DS;

	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_SD;

}



static void hdp_v5_2_update_clock_gating(struct amdgpu_device *adev,

					      bool enable)

{

	hdp_v5_2_update_mem_power_gating(adev, enable);

	hdp_v5_2_update_medium_grain_clock_gating(adev, enable);

}



const struct amdgpu_hdp_funcs hdp_v5_2_funcs = {

	.flush_hdp = hdp_v5_2_flush_hdp,

	.update_clock_gating = hdp_v5_2_update_clock_gating,

	.get_clock_gating_state = hdp_v5_2_get_clockgating_state,

};