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Commit cecbe87d authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0



Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.

Inspired by a patch by Dien Pham in the BSP.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>
parent 5f3a432a
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