Commit ce350c6e authored Jul 09, 2021 by Bindu Ramamurthy Committed by Alex Deucher Jul 21, 2021

drm/amd/display: Populate dtbclk entries for dcn3.02/3.03



[Why]
Populate dtbclk values from bwparams for dcn302, dcn303.

[How]
dtbclk values are fetched from bandwidthparams for all DPM levels and
for DPM levels where smu returns 0, previous level values are reported.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 0f984c94

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -1398,7 +1398,11 @@ void dcn302_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_param
		dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
		dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
		dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
		dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
		/* Populate from bw_params for DTBCLK, SOCCLK */
		if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
		dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
		else
		dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
		if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
		dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
		else

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -1326,7 +1326,11 @@ void dcn303_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_param
		dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
		dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
		dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
		dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
		/* Populate from bw_params for DTBCLK, SOCCLK */
		if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
		dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
		else
		dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
		if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
		dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
		else