Commit 0f984c94 authored by Nevenko Stupar's avatar Nevenko Stupar Committed by Alex Deucher
Browse files

drm/amd/display: Line Buffer changes 



DCN 3x increased Line buffer size for DCHUB latency hiding, from 4 lines
of 4K resolution lines to 5 lines of 4K resolution lines. All Line
Buffer can be used as extended memory for P State change latency hiding.
The maximum number of lines is increased to 32 lines. Finally,
LB_MEMORY_CONFIG_1 (LB memory piece 1) and LB_MEMORY _CONFIG_2 (LB
memory piece 2) are not affected, no change in size, only 3 pieces is
affected, i.e., when all 3 pieces are used in both LB_MEMORY_CONFIG_0
and LB_MEMORY_CONFIG_3 (for 4:2:0) modes.

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6580b28e

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

+6 −1
Original line number Diff line number Diff line
@@ -217,6 +217,8 @@ static void dpp1_dscl_set_lb( 
	const struct line_buffer_params *lb_params,

	enum lb_memory_config mem_size_config)

{

	uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */



	/* LB */

	if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

		/* DSCL caps: pixel data processed in fixed format */
@@ -239,9 +241,12 @@ static void dpp1_dscl_set_lb( 
			LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */

	}



	if (dpp->base.caps->max_lb_partitions == 31)

		max_partitions = 31;



	REG_SET_2(LB_MEMORY_CTRL, 0,

		MEMORY_CONFIG, mem_size_config,

		LB_MAX_PARTITIONS, 63);

		LB_MAX_PARTITIONS, max_partitions);

}



static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c

+0 −16
Original line number Diff line number Diff line
@@ -383,13 +383,6 @@ bool dpp3_get_optimal_number_of_taps( 
	int min_taps_y, min_taps_c;

	enum lb_memory_config lb_config;



	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/

	if (scl_data->viewport.width  != scl_data->h_active &&

		scl_data->viewport.height != scl_data->v_active &&

		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

		scl_data->format == PIXEL_FORMAT_FP16)

		return false;



	if (scl_data->viewport.width > scl_data->h_active &&

		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
@@ -1440,15 +1433,6 @@ bool dpp3_construct( 
	dpp->tf_shift = tf_shift;

	dpp->tf_mask = tf_mask;



	dpp->lb_pixel_depth_supported =

		LB_PIXEL_DEPTH_18BPP |

		LB_PIXEL_DEPTH_24BPP |

		LB_PIXEL_DEPTH_30BPP |

		LB_PIXEL_DEPTH_36BPP;



	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/



	return true;

}

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h

+1 −2
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ 
	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \

	SRI(CURSOR_CONTROL, CURSOR0_, id),\

	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\

	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)



#define DPP_REG_LIST_DCN30(id)\
@@ -163,8 +164,6 @@ 
	SRI(CM_SHAPER_LUT_DATA, CM, id),\

	SRI(CM_MEM_PWR_CTRL2, CM, id), \

	SRI(CM_MEM_PWR_STATUS2, CM, id), \

	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

	SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\

drivers/gpu/drm/amd/display/dc/inc/hw/transform.h

+3 −0
Original line number Diff line number Diff line
@@ -289,6 +289,9 @@ struct dpp_caps { 
	/* DSCL processing pixel data in fixed or float format */

	enum dscl_data_processing_format dscl_data_proc_format;



	/* max LB partitions */

	unsigned int max_lb_partitions;



	/* Calculates the number of partitions in the line buffer.

	 * The implementation of this function is overloaded for

	 * different versions of DSCL LB.