Commit cd48bff7 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/qcom' 

- Add Qualcomm PCIe Endpoint controller driver and DT binding (Manivannan
  Sadhasivam)

- Add qcom struct for device-specific details in match data (Prasad
  Malisetty)

- Switch pcie_1_pipe_clk_src from TCXO to pipe clock after PHY init in
  SC7280 (Prasad Malisetty)

- Add .compatible device ID for SC8180x platform (Bjorn Andersson)

* remotes/lorenzo/pci/qcom:
  PCI: qcom: Add sc8180x compatible
  PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
  PCI: qcom: Replace ops with struct pcie_cfg in pcie match data
  MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding
  PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver
  dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller
parents 83e168d6 45a3ec89

Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm PCIe Endpoint Controller binding



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



allOf:

  - $ref: "pci-ep.yaml#"



properties:

  compatible:

    const: qcom,sdx55-pcie-ep



  reg:

    items:

      - description: Qualcomm-specific PARF configuration registers

      - description: DesignWare PCIe registers

      - description: External local bus interface registers

      - description: Address Translation Unit (ATU) registers

      - description: Memory region used to map remote RC address space

      - description: BAR memory region



  reg-names:

    items:

      - const: parf

      - const: dbi

      - const: elbi

      - const: atu

      - const: addr_space

      - const: mmio



  clocks:

    items:

      - description: PCIe Auxiliary clock

      - description: PCIe CFG AHB clock

      - description: PCIe Master AXI clock

      - description: PCIe Slave AXI clock

      - description: PCIe Slave Q2A AXI clock

      - description: PCIe Sleep clock

      - description: PCIe Reference clock



  clock-names:

    items:

      - const: aux

      - const: cfg

      - const: bus_master

      - const: bus_slave

      - const: slave_q2a

      - const: sleep

      - const: ref



  qcom,perst-regs:

    description: Reference to a syscon representing TCSR followed by the two

                 offsets within syscon for Perst enable and Perst separation

                 enable registers

    $ref: "/schemas/types.yaml#/definitions/phandle-array"

    items:

      minItems: 3

      maxItems: 3



  interrupts:

    items:

      - description: PCIe Global interrupt

      - description: PCIe Doorbell interrupt



  interrupt-names:

    items:

      - const: global

      - const: doorbell



  reset-gpios:

    description: GPIO used as PERST# input signal

    maxItems: 1



  wake-gpios:

    description: GPIO used as WAKE# output signal

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    const: core



  power-domains:

    maxItems: 1



  phys:

    maxItems: 1



  phy-names:

    const: pciephy



  num-lanes:

    default: 2



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - qcom,perst-regs

  - interrupts

  - interrupt-names

  - reset-gpios

  - resets

  - reset-names

  - power-domains



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sdx55.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie_ep: pcie-ep@40000000 {

        compatible = "qcom,sdx55-pcie-ep";

        reg = <0x01c00000 0x3000>,

              <0x40000000 0xf1d>,

              <0x40000f20 0xc8>,

              <0x40001000 0x1000>,

              <0x40002000 0x1000>,

              <0x01c03000 0x3000>;

        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",

                    "mmio";



        clocks = <&gcc GCC_PCIE_AUX_CLK>,

             <&gcc GCC_PCIE_CFG_AHB_CLK>,

             <&gcc GCC_PCIE_MSTR_AXI_CLK>,

             <&gcc GCC_PCIE_SLV_AXI_CLK>,

             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,

             <&gcc GCC_PCIE_SLEEP_CLK>,

             <&gcc GCC_PCIE_0_CLKREF_CLK>;

        clock-names = "aux", "cfg", "bus_master", "bus_slave",

                      "slave_q2a", "sleep", "ref";



        qcom,perst-regs = <&tcsr 0xb258 0xb270>;



        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "global", "doorbell";

        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;

        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;

        resets = <&gcc GCC_PCIE_BCR>;

        reset-names = "core";

        power-domains = <&gcc PCIE_GDSC>;

        phys = <&pcie0_lane>;

        phy-names = "pciephy";

        max-link-speed = <3>;

        num-lanes = <2>;

    };

Documentation/devicetree/bindings/pci/qcom,pcie.txt

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@@ -12,6 +12,7 @@ 
			- "qcom,pcie-ipq4019" for ipq4019

			- "qcom,pcie-ipq8074" for ipq8074

			- "qcom,pcie-qcs404" for qcs404

			- "qcom,pcie-sc8180x" for sc8180x

			- "qcom,pcie-sdm845" for sdm845

			- "qcom,pcie-sm8250" for sm8250

			- "qcom,pcie-ipq6018" for ipq6018
@@ -156,7 +157,7 @@ 
			- "pipe"	PIPE clock



- clock-names:

	Usage: required for sm8250

	Usage: required for sc8180x and sm8250

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary clock
@@ -245,7 +246,7 @@ 
			- "ahb"			AHB reset



- reset-names:

	Usage: required for sdm845 and sm8250

	Usage: required for sc8180x, sdm845 and sm8250

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pci"			PCIe core reset

MAINTAINERS

+9 −1
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@@ -14618,7 +14618,15 @@ M: Stanimir Varbanov <svarbanov@mm-sol.com> 
L:	linux-pci@vger.kernel.org

L:	linux-arm-msm@vger.kernel.org

S:	Maintained

F:	drivers/pci/controller/dwc/*qcom*

F:	drivers/pci/controller/dwc/pcie-qcom.c









PCIE ENDPOINT DRIVER FOR QUALCOMM









M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>









L:	linux-pci@vger.kernel.org









L:	linux-arm-msm@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml









F:	drivers/pci/controller/dwc/pcie-qcom-ep.c

















PCIE DRIVER FOR ROCKCHIP









M:	Shawn Lin <shawn.lin@rock-chips.com>
































drivers/pci/controller/dwc/Kconfig



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@@ -178,6 +178,16 @@ config PCIE_QCOM







	  PCIe controller uses the DesignWare core plus Qualcomm-specific









	  hardware wrappers.



















config PCIE_QCOM_EP









	tristate "Qualcomm PCIe controller - Endpoint mode"









	depends on OF && (ARCH_QCOM || COMPILE_TEST)









	depends on PCI_ENDPOINT









	select PCIE_DW_EP









	help









	  Say Y here to enable support for the PCIe controllers on Qualcomm SoCs









	  to work in endpoint mode. The PCIe controller uses the DesignWare core









	  plus Qualcomm-specific hardware wrappers.



















config PCIE_ARMADA_8K









	bool "Marvell Armada-8K PCIe controller"









	depends on ARCH_MVEBU || COMPILE_TEST
































drivers/pci/controller/dwc/Makefile



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@@ -12,6 +12,7 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o







obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o









obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o









obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o









obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o









obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o









obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o









obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o