Commit 83e168d6 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host/mt7621' 

- Add MediaTek MT7621 SoC PCIe host controller (moved from staging) (Sergio
  Paracuellos)

* pci/host/mt7621:
  MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer
  PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  dt-bindings: PCI: Add MT7621 SoC PCIe host controller

# Conflicts:
#	drivers/pci/controller/Kconfig
#	drivers/pci/controller/Makefile
parents 581e8fce 370ea5aa

Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MT7621 PCIe controller



maintainers:

  - Sergio Paracuellos <sergio.paracuellos@gmail.com>



description: |+

  MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)

  with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: mediatek,mt7621-pci



  reg:

    items:

      - description: host-pci bridge registers

      - description: pcie port 0 RC control registers

      - description: pcie port 1 RC control registers

      - description: pcie port 2 RC control registers



  ranges:

    maxItems: 2



patternProperties:

  'pcie@[0-2],0':

    type: object

    $ref: /schemas/pci/pci-bus.yaml#



    properties:

      resets:

        maxItems: 1



      clocks:

        maxItems: 1



      phys:

        maxItems: 1



    required:

      - "#interrupt-cells"

      - interrupt-map-mask

      - interrupt-map

      - resets

      - clocks

      - phys

      - phy-names

      - ranges



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - ranges

  - "#interrupt-cells"

  - interrupt-map-mask

  - interrupt-map

  - reset-gpios



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/mips-gic.h>



    pcie: pcie@1e140000 {

        compatible = "mediatek,mt7621-pci";

        reg = <0x1e140000 0x100>,

              <0x1e142000 0x100>,

              <0x1e143000 0x100>,

              <0x1e144000 0x100>;



        #address-cells = <3>;

        #size-cells = <2>;

        pinctrl-names = "default";

        pinctrl-0 = <&pcie_pins>;

        device_type = "pci";

        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */

                 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */

        #interrupt-cells = <1>;

        interrupt-map-mask = <0xF800 0 0 0>;

        interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,

                        <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,

                        <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

        reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;



        pcie@0,0 {

            reg = <0x0000 0 0 0 0>;

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0>;

            interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;

            resets = <&rstctrl 24>;

            clocks = <&clkctrl 24>;

            phys = <&pcie0_phy 1>;

            phy-names = "pcie-phy0";

            ranges;

        };



        pcie@1,0 {

            reg = <0x0800 0 0 0 0>;

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0>;

            interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;

            resets = <&rstctrl 25>;

            clocks = <&clkctrl 25>;

            phys = <&pcie0_phy 1>;

            phy-names = "pcie-phy1";

            ranges;

        };



        pcie@2,0 {

            reg = <0x1000 0 0 0 0>;

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0>;

            interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

            resets = <&rstctrl 26>;

            clocks = <&clkctrl 26>;

            phys = <&pcie2_phy 0>;

            phy-names = "pcie-phy2";

            ranges;

        };

    };

...

MAINTAINERS

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@@ -11849,6 +11849,12 @@ S: Maintained 
F:	Documentation/devicetree/bindings/i2c/i2c-mt7621.txt

F:	drivers/i2c/busses/i2c-mt7621.c









MEDIATEK MT7621 PCIE CONTROLLER DRIVER









M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>









S:	Maintained









F:	Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml









F:	drivers/pci/controller/pcie-mt7621.c

















MEDIATEK MT7621 PHY PCI DRIVER









M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>









S:	Maintained
































arch/mips/ralink/Kconfig



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−1






























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@@ -51,7 +51,8 @@ choice







		select SYS_SUPPORTS_HIGHMEM









		select MIPS_GIC









		select CLKSRC_MIPS_GIC









		select HAVE_PCI if PCI_MT7621









		select HAVE_PCI









		select PCI_DRIVERS_GENERIC









		select SOC_BUS









endchoice










































drivers/pci/controller/Kconfig



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@@ -330,6 +330,14 @@ config PCIE_APPLE

















	  If unsure, say Y if you have an Apple Silicon system.



















config PCIE_MT7621









	tristate "MediaTek MT7621 PCIe Controller"









	depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)









	select PHY_MT7621_PCI









	default SOC_MT7621









	help









	  This selects a driver for the MediaTek MT7621 PCIe Controller.



















source "drivers/pci/controller/dwc/Kconfig"









source "drivers/pci/controller/mobiveil/Kconfig"









source "drivers/pci/controller/cadence/Kconfig"
































drivers/pci/controller/Makefile



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@@ -38,6 +38,8 @@ obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o







obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o









obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o









obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o









obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o



















# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW









obj-y				+= dwc/









obj-y				+= mobiveil/