Commit ccc6e8a1 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Bjorn Andersson
Browse files

arm64: dts: sc7180: Add sdhc opps and power-domains 



Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sc7180.

Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 6123e744

arch/arm64/boot/dts/qcom/sc7180.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -684,6 +684,8 @@ 
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

					<&gcc GCC_SDCC1_AHB_CLK>;

			clock-names = "core", "iface";

			power-domains = <&rpmhpd SC7180_CX>;

			operating-points-v2 = <&sdhc1_opp_table>;



			bus-width = <8>;

			non-removable;
@@ -695,6 +697,20 @@ 
			mmc-hs400-enhanced-strobe;



			status = "disabled";



			sdhc1_opp_table: sdhc1-opp-table {

				compatible = "operating-points-v2";



				opp-100000000 {

					opp-hz = /bits/ 64 <100000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

				};



				opp-384000000 {

					opp-hz = /bits/ 64 <384000000>;

					required-opps = <&rpmhpd_opp_svs_l1>;

				};

			};

		};



		qup_opp_table: qup-opp-table {
@@ -2460,10 +2476,26 @@ 
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

					<&gcc GCC_SDCC2_AHB_CLK>;

			clock-names = "core", "iface";

			power-domains = <&rpmhpd SC7180_CX>;

			operating-points-v2 = <&sdhc2_opp_table>;



			bus-width = <4>;



			status = "disabled";



			sdhc2_opp_table: sdhc2-opp-table {

				compatible = "operating-points-v2";



				opp-100000000 {

					opp-hz = /bits/ 64 <100000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

				};



				opp-202000000 {

					opp-hz = /bits/ 64 <202000000>;

					required-opps = <&rpmhpd_opp_svs_l1>;

				};

			};

		};



		qspi_opp_table: qspi-opp-table {