Commit cc6f88b9 authored by Kieran Bingham's avatar Kieran Bingham Committed by Laurent Pinchart
Browse files

drm: rcar-du: Split CRTC IRQ and Clock features 



Not all platforms require both per-crtc IRQ and per-crtc clock
management. In preparation for suppporting such platforms, split the
feature macro to be able to specify both features independently.

The other features are incremented accordingly, to keep the two crtc
features adjacent.

Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarKieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent 8c252d3b

drivers/gpu/drm/rcar-du/rcar_du_crtc.c

+2 −2
Original line number Diff line number Diff line
@@ -1206,7 +1206,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, 
	int ret;



	/* Get the CRTC clock and the optional external clock. */

	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {

	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_CLOCK)) {

		sprintf(clk_name, "du.%u", hwindex);

		name = clk_name;

	} else {
@@ -1272,7 +1272,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, 
	drm_crtc_helper_add(crtc, &crtc_helper_funcs);



	/* Register the interrupt handler. */

	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {

	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ)) {

		/* The IRQ's are associated with the CRTC (sw)index. */

		irq = platform_get_irq(pdev, swindex);

		irqflags = 0;

drivers/gpu/drm/rcar-du/rcar_du_drv.c

+32 −16
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ 


static const struct rcar_du_device_info rzg1_du_r8a7743_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -59,7 +60,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = { 


static const struct rcar_du_device_info rzg1_du_r8a7745_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -80,7 +82,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { 


static const struct rcar_du_device_info rzg1_du_r8a77470_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -106,7 +109,8 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = { 


static const struct rcar_du_device_info rcar_du_r8a774a1_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -135,7 +139,8 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = { 


static const struct rcar_du_device_info rcar_du_r8a774b1_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -164,7 +169,8 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = { 


static const struct rcar_du_device_info rcar_du_r8a774c0_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE,

	.channels_mask = BIT(1) | BIT(0),

	.routes = {
@@ -190,7 +196,8 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = { 


static const struct rcar_du_device_info rcar_du_r8a774e1_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -240,7 +247,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = { 


static const struct rcar_du_device_info rcar_du_r8a7790_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.quirks = RCAR_DU_QUIRK_ALIGN_128B,
@@ -270,7 +278,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { 
/* M2-W (r8a7791) and M2-N (r8a7793) are identical */

static const struct rcar_du_device_info rcar_du_r8a7791_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -293,7 +302,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { 


static const struct rcar_du_device_info rcar_du_r8a7792_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -312,7 +322,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = { 


static const struct rcar_du_device_info rcar_du_r8a7794_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),
@@ -334,7 +345,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = { 


static const struct rcar_du_device_info rcar_du_r8a7795_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -367,7 +379,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { 


static const struct rcar_du_device_info rcar_du_r8a7796_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -396,7 +409,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { 


static const struct rcar_du_device_info rcar_du_r8a77965_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -425,7 +439,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = { 


static const struct rcar_du_device_info rcar_du_r8a77970_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,
@@ -449,7 +464,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { 


static const struct rcar_du_device_info rcar_du_r8a7799x_info = {

	.gen = 3,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_CRTC_CLOCK

		  | RCAR_DU_FEATURE_VSP1_SOURCE,

	.channels_mask = BIT(1) | BIT(0),

	.routes = {

drivers/gpu/drm/rcar-du/rcar_du_drv.h

+5 −4
Original line number Diff line number Diff line
@@ -26,10 +26,11 @@ struct drm_bridge; 
struct drm_property;

struct rcar_du_device;



#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK	BIT(0)	/* Per-CRTC IRQ and clock */

#define RCAR_DU_FEATURE_VSP1_SOURCE	BIT(1)	/* Has inputs from VSP1 */

#define RCAR_DU_FEATURE_INTERLACED	BIT(2)	/* HW supports interlaced */

#define RCAR_DU_FEATURE_TVM_SYNC	BIT(3)	/* Has TV switch/sync modes */

#define RCAR_DU_FEATURE_CRTC_IRQ	BIT(0)	/* Per-CRTC IRQ */

#define RCAR_DU_FEATURE_CRTC_CLOCK	BIT(1)	/* Per-CRTC clock */

#define RCAR_DU_FEATURE_VSP1_SOURCE	BIT(2)	/* Has inputs from VSP1 */

#define RCAR_DU_FEATURE_INTERLACED	BIT(3)	/* HW supports interlaced */

#define RCAR_DU_FEATURE_TVM_SYNC	BIT(4)	/* Has TV switch/sync modes */



#define RCAR_DU_QUIRK_ALIGN_128B	BIT(0)	/* Align pitches to 128 bytes */