Commit cbea5639 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/cstate: Add Rocket Lake CPU support 



From the perspective of Intel cstate residency counters, Rocket Lake is
the same as Ice Lake and Tiger Lake. Share the code with them. Update
the comments for Rocket Lake.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201019153528.13850-2-kan.liang@linux.intel.com
parent b14d0db5

arch/x86/events/intel/cstate.c

+10 −9
Original line number Diff line number Diff line
@@ -51,46 +51,46 @@ 
 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *						TNT,RKL

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,

 *						ICL,TGL

 *						ICL,TGL,RKL

 *			       Scope: Core

 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML,ICL,TGL,TNT

 *						KBL,CML,ICL,TGL,TNT,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL,KBL,CML,ICL,TGL,TNT

 *						GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *						TNT,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,

 *						KBL,CML,ICL,TGL

 *						KBL,CML,ICL,TGL,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.

 *			       perf code: 0x04

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.

 *			       perf code: 0x05

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,

 *						TNT

 *						TNT,RKL

 *			       Scope: Package (physical package)

 *

 */
@@ -649,6 +649,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&icl_cstates),

	{ },

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);