Commit c974a8e5 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/perf' into for-next/core 

Perf and PMU updates including support for Cortex-A78 and the v8.3 SPE
extensions.

* for-next/perf:
  drivers/perf: Replace spin_lock_irqsave to spin_lock
  dt-bindings: arm: add Cortex-A78 binding
  arm64: perf: add support for Cortex-A78
  arm64: perf: Constify static attribute_group structs
  drivers/perf: Prevent forced unbinding of ARM_DMC620_PMU drivers
  perf/arm-cmn: Move IRQs when migrating context
  perf/arm-cmn: Fix PMU instance naming
  perf: Constify static struct attribute_group
  perf: hisi: Constify static struct attribute_group
  perf/imx_ddr: Constify static struct attribute_group
  perf: qcom: Constify static struct attribute_group
  drivers/perf: Add support for ARMv8.3-SPE
parents 1d32854e 8ee37e0f

Documentation/admin-guide/perf/arm-cmn.rst

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ PMU events 
----------



The PMU driver registers a single PMU device for the whole interconnect,

see /sys/bus/event_source/devices/arm_cmn. Multi-chip systems may link

see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link

more than one CMN together via external CCIX links - in this situation,

each mesh counts its own events entirely independently, and additional

PMU devices will be named arm_cmn_{1..n}.

Documentation/devicetree/bindings/arm/pmu.yaml

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ properties: 
          - arm,cortex-a75-pmu

          - arm,cortex-a76-pmu

          - arm,cortex-a77-pmu

          - arm,cortex-a78-pmu

          - arm,neoverse-e1-pmu

          - arm,neoverse-n1-pmu

          - brcm,vulcan-pmu

arch/arm64/include/asm/sysreg.h

+8 −1
Original line number Diff line number Diff line
@@ -291,7 +291,11 @@ 
#define SYS_PMSFCR_EL1_ST_SHIFT		18



#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)

#define SYS_PMSEVFR_EL1_RES0		0x0000ffff00ff0f55UL

#define SYS_PMSEVFR_EL1_RES0_8_2	\

	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\

	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))

#define SYS_PMSEVFR_EL1_RES0_8_3	\

	(SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))



#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)

#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
@@ -844,6 +848,9 @@ 
#define ID_AA64DFR0_PMUVER_8_5		0x6

#define ID_AA64DFR0_PMUVER_IMP_DEF	0xf



#define ID_AA64DFR0_PMSVER_8_2		0x1

#define ID_AA64DFR0_PMSVER_8_3		0x2



#define ID_DFR0_PERFMON_SHIFT		24



#define ID_DFR0_PERFMON_8_1		0x4

arch/arm64/kernel/perf_event.c

+10 −3
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj, 
	return 0;

}



static struct attribute_group armv8_pmuv3_events_attr_group = {

static const struct attribute_group armv8_pmuv3_events_attr_group = {

	.name = "events",

	.attrs = armv8_pmuv3_event_attrs,

	.is_visible = armv8pmu_event_attr_is_visible,
@@ -300,7 +300,7 @@ static struct attribute *armv8_pmuv3_format_attrs[] = { 
	NULL,

};



static struct attribute_group armv8_pmuv3_format_attr_group = {

static const struct attribute_group armv8_pmuv3_format_attr_group = {

	.name = "format",

	.attrs = armv8_pmuv3_format_attrs,

};
@@ -322,7 +322,7 @@ static struct attribute *armv8_pmuv3_caps_attrs[] = { 
	NULL,

};



static struct attribute_group armv8_pmuv3_caps_attr_group = {

static const struct attribute_group armv8_pmuv3_caps_attr_group = {

	.name = "caps",

	.attrs = armv8_pmuv3_caps_attrs,

};
@@ -1188,6 +1188,12 @@ static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu) 
				       armv8_pmuv3_map_event);

}



static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",

				       armv8_pmuv3_map_event);

}



static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
@@ -1225,6 +1231,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { 
	{.compatible = "arm,cortex-a75-pmu",	.data = armv8_a75_pmu_init},

	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},

	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},

	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},

	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},

	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},

	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},

drivers/perf/arm-cci.c

+3 −4
Original line number Diff line number Diff line
@@ -1026,12 +1026,11 @@ static void pmu_event_set_period(struct perf_event *event) 


static irqreturn_t pmu_handle_irq(int irq_num, void *dev)

{

	unsigned long flags;

	struct cci_pmu *cci_pmu = dev;

	struct cci_pmu_hw_events *events = &cci_pmu->hw_events;

	int idx, handled = IRQ_NONE;



	raw_spin_lock_irqsave(&events->pmu_lock, flags);

	raw_spin_lock(&events->pmu_lock);



	/* Disable the PMU while we walk through the counters */

	__cci_pmu_disable(cci_pmu);
@@ -1061,7 +1060,7 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev) 


	/* Enable the PMU and sync possibly overflowed counters */

	__cci_pmu_enable_sync(cci_pmu);

	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);

	raw_spin_unlock(&events->pmu_lock);



	return IRQ_RETVAL(handled);

}
@@ -1376,7 +1375,7 @@ static struct attribute *pmu_attrs[] = { 
	NULL,

};



static struct attribute_group pmu_attr_group = {

static const struct attribute_group pmu_attr_group = {

	.attrs = pmu_attrs,

};