Commit 1d32854e authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/misc' into for-next/core 

Miscellaneous arm64 changes for 5.12.

* for-next/misc:
  arm64: Make CPU_BIG_ENDIAN depend on ld.bfd or ld.lld 13.0.0+
  arm64: vmlinux.ld.S: add assertion for tramp_pg_dir offset
  arm64: vmlinux.ld.S: add assertion for reserved_pg_dir offset
  arm64/ptdump:display the Linear Mapping start marker
  arm64: ptrace: Fix missing return in hw breakpoint code
  KVM: arm64: Move __hyp_set_vectors out of .hyp.text
  arm64: Include linux/io.h in mm/mmap.c
  arm64: cacheflush: Remove stale comment
  arm64: mm: Remove unused header file
  arm64/sparsemem: reduce SECTION_SIZE_BITS
  arm64/mm: Add warning for outside range requests in vmemmap_populate()
  arm64: Drop workaround for broken 'S' constraint with GCC 4.9
parents b374d0f9 e9c6deee

arch/arm64/Kconfig

+3 −2
Original line number Diff line number Diff line
@@ -953,6 +953,7 @@ choice 


config CPU_BIG_ENDIAN

	bool "Build big-endian kernel"

	depends on !LD_IS_LLD || LLD_VERSION >= 130000

	help

	  Say Y if you plan on running a kernel with a big-endian userspace.

arch/arm64/include/asm/asm-uaccess.h

+2 −2
Original line number Diff line number Diff line
@@ -15,10 +15,10 @@ 
	.macro	__uaccess_ttbr0_disable, tmp1

	mrs	\tmp1, ttbr1_el1			// swapper_pg_dir

	bic	\tmp1, \tmp1, #TTBR_ASID_MASK

	sub	\tmp1, \tmp1, #PAGE_SIZE		// reserved_pg_dir just before swapper_pg_dir

	sub	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET	// reserved_pg_dir

	msr	ttbr0_el1, \tmp1			// set reserved TTBR0_EL1

	isb

	add	\tmp1, \tmp1, #PAGE_SIZE

	add	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET

	msr	ttbr1_el1, \tmp1		// set reserved ASID

	isb

	.endm

arch/arm64/include/asm/cacheflush.h

+0 −5
Original line number Diff line number Diff line
@@ -30,11 +30,6 @@ 
 *	the implementation assumes non-aliasing VIPT D-cache and (aliasing)

 *	VIPT I-cache.

 *

 *	flush_cache_mm(mm)

 *

 *		Clean and invalidate all user space cache entries

 *		before a change of page tables.

 *

 *	flush_icache_range(start, end)

 *

 *		Ensure coherency between the I-cache and the D-cache in the

arch/arm64/include/asm/kvm_asm.h

+1 −7
Original line number Diff line number Diff line
@@ -199,12 +199,6 @@ extern void __vgic_v3_init_lrs(void); 


extern u32 __kvm_get_mdcr_el2(void);



#if defined(GCC_VERSION) && GCC_VERSION < 50000

#define SYM_CONSTRAINT	"i"

#else

#define SYM_CONSTRAINT	"S"

#endif



/*

 * Obtain the PC-relative address of a kernel symbol

 * s: symbol
@@ -221,7 +215,7 @@ extern u32 __kvm_get_mdcr_el2(void); 
		typeof(s) *addr;					\

		asm("adrp	%0, %1\n"				\

		    "add	%0, %0, :lo12:%1\n"			\

		    : "=r" (addr) : SYM_CONSTRAINT (&s));		\

		    : "=r" (addr) : "S" (&s));				\

		addr;							\

	})

arch/arm64/include/asm/memory.h

+12 −0
Original line number Diff line number Diff line
@@ -159,6 +159,18 @@ 
#define IOREMAP_MAX_ORDER	(PMD_SHIFT)

#endif



/*

 *  Open-coded (swapper_pg_dir - reserved_pg_dir) as this cannot be calculated

 *  until link time.

 */

#define RESERVED_SWAPPER_OFFSET	(PAGE_SIZE)



/*

 *  Open-coded (swapper_pg_dir - tramp_pg_dir) as this cannot be calculated

 *  until link time.

 */

#define TRAMP_SWAPPER_OFFSET	(2 * PAGE_SIZE)



#ifndef __ASSEMBLY__



#include <linux/bitops.h>