Commit c931ef00 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Program VLV/CHV PIPE_MSA_MISC register 



VLV/CHV have an extra register to configure some stereo3d
signalling details via DP MSA. Make sure we reset that
register to zero (since we don't do any stereo3d stuff).

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
parent 6e889b1c

drivers/gpu/drm/i915/display/intel_display.c

+2 −0
Original line number Diff line number Diff line
@@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, 


	intel_set_pipe_src_size(new_crtc_state);



	intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);



	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

		intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);

		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -7574,6 +7574,12 @@ enum skl_power_gate { 
#define PIPE_FLIPDONETIMSTMP(pipe)	\

	_MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)



#define _VLV_PIPE_MSA_MISC_A			0x70048

#define VLV_PIPE_MSA_MISC(pipe)		\

			_MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)

#define   VLV_MSA_MISC1_HW_ENABLE			REG_BIT(31)

#define   VLV_MSA_MISC1_SW_S3D_MASK			REG_GENMASK(2, 0) /* MSA MISC1 3:1 */



#define GGC				_MMIO(0x108040)

#define   GMS_MASK			REG_GENMASK(15, 8)

#define   GGMS_MASK			REG_GENMASK(7, 6)