Commit c8b1d0fe authored by Leo Chen's avatar Leo Chen Committed by Alex Deucher
Browse files

drm/amd/display: Adding log clock table from SMU 



[Why & How]
Adding log for clock table from SMU helps with the debugging process.
Implemented using DC_LOG_SMU to output log.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarLeo Chen <sancchen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 74f4e84d

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+46 −0
Original line number Diff line number Diff line
@@ -48,6 +48,11 @@ 


#include "dc_dmub_srv.h"



#include "logger_types.h"

#undef DC_LOGGER

#define DC_LOGGER \

	clk_mgr->base.base.ctx->logger



#include "yellow_carp_offset.h"



#define regCLK1_CLK_PLL_REQ			0x0237
@@ -737,8 +742,49 @@ void dcn31_clk_mgr_construct( 
	clk_mgr->base.base.bw_params = &dcn31_bw_params;



	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

		int i;



		dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);



		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

				   "NumDispClkLevelsEnabled: %d\n"

				   "NumSocClkLevelsEnabled: %d\n"

				   "VcnClkLevelsEnabled: %d\n"

				   "NumDfPst atesEnabled: %d\n"

				   "MinGfxClk: %d\n"

				   "MaxGfxClk: %d\n",

				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

				   smu_dpm_clks.dpm_clks->MinGfxClk,

				   smu_dpm_clks.dpm_clks->MaxGfxClk);

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

					   i,

					   smu_dpm_clks.dpm_clks->DcfClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);

		}

		for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);



		for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

		}

		if (ctx->dc_bios && ctx->dc_bios->integrated_info) {

			dcn31_clk_mgr_helper_populate_bw_params(

					&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+48 −0
Original line number Diff line number Diff line
@@ -51,6 +51,13 @@ 
#include "dc_link_dp.h"

#include "dcn314_smu.h"





#include "logger_types.h"

#undef DC_LOGGER

#define DC_LOGGER \

	clk_mgr->base.base.ctx->logger





#define MAX_INSTANCE                                        7

#define MAX_SEGMENT                                         8
@@ -775,7 +782,48 @@ void dcn314_clk_mgr_construct( 
	clk_mgr->base.base.bw_params = &dcn314_bw_params;



	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

		int i;



		dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

				   "NumDispClkLevelsEnabled: %d\n"

				   "NumSocClkLevelsEnabled: %d\n"

				   "VcnClkLevelsEnabled: %d\n"

				   "NumDfPst atesEnabled: %d\n"

				   "MinGfxClk: %d\n"

				   "MaxGfxClk: %d\n",

				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

				   smu_dpm_clks.dpm_clks->MinGfxClk,

				   smu_dpm_clks.dpm_clks->MaxGfxClk);

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

					   i,

					   smu_dpm_clks.dpm_clks->DcfClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);

		}

		for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);



		for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

		}



		if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

			dcn314_clk_mgr_helper_populate_bw_params(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+46 −0
Original line number Diff line number Diff line
@@ -41,6 +41,11 @@ 


#include "dc_dmub_srv.h"



#include "logger_types.h"

#undef DC_LOGGER

#define DC_LOGGER \

	clk_mgr->base.base.ctx->logger



#include "dc_link_dp.h"



#define TO_CLK_MGR_DCN315(clk_mgr)\
@@ -666,7 +671,48 @@ void dcn315_clk_mgr_construct( 
	clk_mgr->base.base.bw_params = &dcn315_bw_params;



	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

		int i;



		dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

				   "NumDispClkLevelsEnabled: %d\n"

				   "NumSocClkLevelsEnabled: %d\n"

				   "VcnClkLevelsEnabled: %d\n"

				   "NumDfPst atesEnabled: %d\n"

				   "MinGfxClk: %d\n"

				   "MaxGfxClk: %d\n",

				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

				   smu_dpm_clks.dpm_clks->MinGfxClk,

				   smu_dpm_clks.dpm_clks->MaxGfxClk);

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

					   i,

					   smu_dpm_clks.dpm_clks->DcfClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);

		}

		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);

		}

		for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)

			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);



		for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

			DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"

					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

		}



		if (ctx->dc_bios && ctx->dc_bios->integrated_info) {

			dcn315_clk_mgr_helper_populate_bw_params(