Commit c888b7bd authored by Mark Rutland's avatar Mark Rutland Committed by Catalin Marinas
Browse files

arm64: rename ARM64_HAS_IRQ_PRIO_MASKING to ARM64_HAS_GIC_PRIO_MASKING 



Subsequent patches will add more GIC-related cpucaps. When we do so, it
would be nice to give them a consistent HAS_GIC_* prefix.

In preparation for doing so, this patch renames the existing
ARM64_HAS_IRQ_PRIO_MASKING cap to ARM64_HAS_GIC_PRIO_MASKING.

The cpucaps file was hand-modified; all other changes were scripted
with:

  find . -type f -name '*.[chS]' -print0 | \
    xargs -0 sed -i 's/ARM64_HAS_IRQ_PRIO_MASKING/ARM64_HAS_GIC_PRIO_MASKING/'

There should be no functional change as a result of this patch.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20230130145429.903791-3-mark.rutland@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 0e62ccb9

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -806,7 +806,7 @@ static inline bool system_has_full_ptr_auth(void) 
static __always_inline bool system_uses_irq_prio_masking(void)

{

	return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&

	       cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);

	       cpus_have_const_cap(ARM64_HAS_GIC_PRIO_MASKING);

}



static inline bool system_supports_mte(void)

arch/arm64/include/asm/irqflags.h

+5 −5
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ static inline void arch_local_irq_enable(void) 
	asm volatile(ALTERNATIVE(

		"msr	daifclr, #3		// arch_local_irq_enable",

		__msr_s(SYS_ICC_PMR_EL1, "%0"),

		ARM64_HAS_IRQ_PRIO_MASKING)

		ARM64_HAS_GIC_PRIO_MASKING)

		:

		: "r" ((unsigned long) GIC_PRIO_IRQON)

		: "memory");
@@ -54,7 +54,7 @@ static inline void arch_local_irq_disable(void) 
	asm volatile(ALTERNATIVE(

		"msr	daifset, #3		// arch_local_irq_disable",

		__msr_s(SYS_ICC_PMR_EL1, "%0"),

		ARM64_HAS_IRQ_PRIO_MASKING)

		ARM64_HAS_GIC_PRIO_MASKING)

		:

		: "r" ((unsigned long) GIC_PRIO_IRQOFF)

		: "memory");
@@ -70,7 +70,7 @@ static inline unsigned long arch_local_save_flags(void) 
	asm volatile(ALTERNATIVE(

		"mrs	%0, daif",

		__mrs_s("%0", SYS_ICC_PMR_EL1),

		ARM64_HAS_IRQ_PRIO_MASKING)

		ARM64_HAS_GIC_PRIO_MASKING)

		: "=&r" (flags)

		:

		: "memory");
@@ -85,7 +85,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) 
	asm volatile(ALTERNATIVE(

		"and	%w0, %w1, #" __stringify(PSR_I_BIT),

		"eor	%w0, %w1, #" __stringify(GIC_PRIO_IRQON),

		ARM64_HAS_IRQ_PRIO_MASKING)

		ARM64_HAS_GIC_PRIO_MASKING)

		: "=&r" (res)

		: "r" ((int) flags)

		: "memory");
@@ -122,7 +122,7 @@ static inline void arch_local_irq_restore(unsigned long flags) 
	asm volatile(ALTERNATIVE(

		"msr	daif, %0",

		__msr_s(SYS_ICC_PMR_EL1, "%0"),

		ARM64_HAS_IRQ_PRIO_MASKING)

		ARM64_HAS_GIC_PRIO_MASKING)

		:

		: "r" (flags)

		: "memory");

arch/arm64/include/asm/ptrace.h

+1 −1
Original line number Diff line number Diff line
@@ -194,7 +194,7 @@ struct pt_regs { 
	u32 unused2;

#endif

	u64 sdei_ttbr1;

	/* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */

	/* Only valid when ARM64_HAS_GIC_PRIO_MASKING is enabled. */

	u64 pmr_save;

	u64 stackframe[2];

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -2534,7 +2534,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		 * Depends on having GICv3

		 */

		.desc = "IRQ priority masking",

		.capability = ARM64_HAS_IRQ_PRIO_MASKING,

		.capability = ARM64_HAS_GIC_PRIO_MASKING,

		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,

		.matches = can_use_gic_priorities,

		.sys_reg = SYS_ID_AA64PFR0_EL1,

arch/arm64/kernel/entry.S

+2 −2
Original line number Diff line number Diff line
@@ -312,7 +312,7 @@ alternative_else_nop_endif 


#ifdef CONFIG_ARM64_PSEUDO_NMI

	/* Save pmr */

alternative_if ARM64_HAS_IRQ_PRIO_MASKING

alternative_if ARM64_HAS_GIC_PRIO_MASKING

	mrs_s	x20, SYS_ICC_PMR_EL1

	str	x20, [sp, #S_PMR_SAVE]

	mov	x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
@@ -337,7 +337,7 @@ alternative_else_nop_endif 


#ifdef CONFIG_ARM64_PSEUDO_NMI

	/* Restore pmr */

alternative_if ARM64_HAS_IRQ_PRIO_MASKING

alternative_if ARM64_HAS_GIC_PRIO_MASKING

	ldr	x20, [sp, #S_PMR_SAVE]

	msr_s	SYS_ICC_PMR_EL1, x20

	mrs_s	x21, SYS_ICC_CTLR_EL1