Commit 0e62ccb9 authored by Mark Rutland's avatar Mark Rutland Committed by Catalin Marinas
Browse files

arm64: rename ARM64_HAS_SYSREG_GIC_CPUIF to ARM64_HAS_GIC_CPUIF_SYSREGS 



Subsequent patches will add more GIC-related cpucaps. When we do so, it
would be nice to give them a consistent HAS_GIC_* prefix.

In preparation for doing so, this patch renames the existing
ARM64_HAS_SYSREG_GIC_CPUIF cap to ARM64_HAS_GIC_CPUIF_SYSREGS.

The 'CPUIF_SYSREGS' suffix is chosen so that this will be ordered ahead
of other ARM64_HAS_GIC_* definitions in subsequent patches.

The cpucaps file was hand-modified; all other changes were scripted
with:

  find . -type f -name '*.[chS]' -print0 | \
    xargs -0 sed -i
    's/ARM64_HAS_SYSREG_GIC_CPUIF/ARM64_HAS_GIC_CPUIF_SYSREGS/'

There should be no functional change as a result of this patch.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20230130145429.903791-2-mark.rutland@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b7bfaa76

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -2142,7 +2142,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
	},

	{

		.desc = "GIC system register CPU interface",

		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,

		.capability = ARM64_HAS_GIC_CPUIF_SYSREGS,

		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,

		.matches = has_useable_gicv3_cpuif,

		.sys_reg = SYS_ID_AA64PFR0_EL1,

arch/arm64/tools/cpucaps

+1 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ HAS_GENERIC_AUTH 
HAS_GENERIC_AUTH_ARCH_QARMA3

HAS_GENERIC_AUTH_ARCH_QARMA5

HAS_GENERIC_AUTH_IMP_DEF

HAS_GIC_CPUIF_SYSREGS

HAS_IRQ_PRIO_MASKING

HAS_LDAPR

HAS_LSE_ATOMICS
@@ -38,7 +39,6 @@ HAS_RAS_EXTN 
HAS_RNG

HAS_SB

HAS_STAGE2_FWB

HAS_SYSREG_GIC_CPUIF

HAS_TIDCP1

HAS_TLB_RANGE

HAS_VIRT_HOST_EXTN

drivers/irqchip/irq-gic.c

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 


static void gic_check_cpu_features(void)

{

	WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),

	WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS),

			TAINT_CPU_OUT_OF_SPEC,

			"GICv3 system registers enabled, broken firmware!\n");

}