Commit c7930112 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.15 kernel cycle, no
  core changes at all this time, just driver work!

  New drivers:

   - New subdriver for Intel Keem Bay (an ARM-based SoC)

   - New subdriver for Qualcomm MDM9607 and SM6115

   - New subdriver for ST Microelectronics STM32MP135

   - New subdriver for Freescale i.MX8ULP ("Ultra Low Power")

   - New subdriver for Ingenic X2100

   - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO

   - Support Samsung Exynos850

   - Support Renesas RZ/G2L

  Enhancements:

   - A major refactoring of the Rockchip driver, breaking part of it out
     to a separate GPIO driver in drivers/gpio

   - Pin bias support on Renesas r8a77995

   - Add SCI pins support to Ingenic JZ4755 and JZ4760

   - Mediatek device tree bindings converted to YAML"

* tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits)
  pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
  pinctrl: samsung: Add Exynos850 SoC specific data
  dt-bindings: pinctrl: samsung: Add Exynos850 doc
  MAINTAINERS: Add maintainers for amd-pinctrl driver
  pinctrl: Add Intel Keem Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
  pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device
  dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property
  dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML
  dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments
  dt-bindings: mediatek: convert pinctrl to yaml
  arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl
  arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl
  pinctrl: ingenic: Add .max_register in regmap_config
  pinctrl: ingenic: Fix bias config for X2000(E)
  pinctrl: ingenic: Fix incorrect pull up/down info
  pinctrl: Ingenic: Add pinctrl driver for X2100.
  dt-bindings: pinctrl: Add bindings for Ingenic X2100.
  pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.
  pinctrl: Ingenic: Improve the code.
  ...
parents 75d6e7d9 04853352

Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8ULP IOMUX Controller



maintainers:

  - Jacky Bai <ping.bai@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8ulp-iomuxc1



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 5 integers and represents the mux and config

          setting for one pin. The first 4 integers <mux_config_reg input_reg

          mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8ULP Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_config_reg" indicates the offset of mux register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_mode" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@298c0000 {

        compatible = "fsl,imx8ulp-iomuxc1";

        reg = <0x298c0000 0x10000>;



        pinctrl_lpuart5: lpuart5grp {

            fsl,pins =

                <0x0138 0x08F0 0x4 0x3	0x3>,

                <0x013C 0x08EC 0x4 0x3	0x3>;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml

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@@ -19,10 +19,10 @@ description: > 
  pin within that GPIO port. For example PA0 is the first pin in GPIO port A,

  and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,

  the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128

  pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.

  The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO

  ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,

  PA to PG, for a total of 224 pins.

  pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of

  160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains

  6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO

  ports, PA to PG, for a total of 224 pins.



maintainers:

  - Paul Cercueil <paul@crapouillou.net>
@@ -47,6 +47,7 @@ properties: 
          - ingenic,x1500-pinctrl

          - ingenic,x1830-pinctrl

          - ingenic,x2000-pinctrl

          - ingenic,x2100-pinctrl

      - items:

          - const: ingenic,jz4760b-pinctrl

          - const: ingenic,jz4760-pinctrl
@@ -85,6 +86,7 @@ patternProperties: 
          - ingenic,x1500-gpio

          - ingenic,x1830-gpio

          - ingenic,x2000-gpio

          - ingenic,x2100-gpio



      reg:

        items:

Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Keem Bay pin controller Device Tree Bindings



maintainers:

  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>



description: |

  Intel Keem Bay SoC integrates a pin controller which enables control

  of pin directions, input/output values and configuration

  for a total of 80 pins.



properties:

  compatible:

    const: intel,keembay-pinctrl



  reg:

    maxItems: 2



  gpio-controller: true



  '#gpio-cells':

    const: 2



  ngpios:

    description: The number of GPIOs exposed.

    const: 80



  interrupts:

    description:

      Specifies the interrupt lines to be used by the controller.

      Each interrupt line is shared by upto 4 GPIO lines.

    maxItems: 8



  interrupt-controller: true



  '#interrupt-cells':

    const: 2



patternProperties:

  '^gpio@[0-9a-f]*$':

    type: object



    description:

      Child nodes can be specified to contain pin configuration information,

      which can then be utilized by pinctrl client devices.

      The following properties are supported.



    properties:

      pins:

        description: |

          The name(s) of the pins to be configured in the child node.

          Supported pin names are "GPIO0" up to "GPIO79".



      bias-disable: true



      bias-pull-down: true



      bias-pull-up: true



      drive-strength:

        description: IO pads drive strength in milli Ampere.

        enum: [2, 4, 8, 12]



      bias-bus-hold:

        type: boolean



      input-schmitt-enable:

        type: boolean



      slew-rate:

        description: GPIO slew rate control.

                      0 - Fast(~100MHz)

                      1 - Slow(~50MHz)

        enum: [0, 1]



additionalProperties: false



required:

  - compatible

  - reg

  - gpio-controller

  - ngpios

  - '#gpio-cells'

  - interrupts

  - interrupt-controller

  - '#interrupt-cells'



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    // Example 1

    gpio@0 {

        compatible = "intel,keembay-pinctrl";

        reg = <0x600b0000 0x88>,

              <0x600b0190 0x1ac>;

        gpio-controller;

        ngpios = <0x50>;

        #gpio-cells = <0x2>;

        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };



    // Example 2

    gpio@1 {

        compatible = "intel,keembay-pinctrl";

        reg = <0x600c0000 0x88>,

              <0x600c0190 0x1ac>;

        gpio-controller;

        ngpios = <0x50>;

        #gpio-cells = <0x2>;

        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };

Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt

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@@ -43,19 +43,19 @@ group emmc_nb 


group pwm0

 - pin 11 (GPIO1-11)

 - functions pwm, gpio

 - functions pwm, led, gpio



group pwm1

 - pin 12

 - functions pwm, gpio

 - functions pwm, led, gpio



group pwm2

 - pin 13

 - functions pwm, gpio

 - functions pwm, led, gpio



group pwm3

 - pin 14

 - functions pwm, gpio

 - functions pwm, led, gpio



group pmic1

 - pin 7

Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek MT65xx Pin Controller Device Tree Bindings



maintainers:

  - Sean Wang <sean.wang@kernel.org>



description: |+

  The Mediatek's Pin controller is used to control SoC pins.



properties:

  compatible:

    enum:

      - mediatek,mt2701-pinctrl

      - mediatek,mt2712-pinctrl

      - mediatek,mt6397-pinctrl

      - mediatek,mt7623-pinctrl

      - mediatek,mt8127-pinctrl

      - mediatek,mt8135-pinctrl

      - mediatek,mt8167-pinctrl

      - mediatek,mt8173-pinctrl

      - mediatek,mt8516-pinctrl



  reg:

    maxItems: 1



  pins-are-numbered:

    $ref: /schemas/types.yaml#/definitions/flag

    description: |

      Specify the subnodes are using numbered pinmux to specify pins.



  gpio-controller: true



  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.



  mediatek,pctl-regmap:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    minItems: 1

    maxItems: 2

    description: |

      Should be phandles of the syscfg node.



  interrupt-controller: true



  interrupts:

    minItems: 1

    maxItems: 3



  "#interrupt-cells":

    const: 2



required:

  - compatible

  - pins-are-numbered

  - gpio-controller

  - "#gpio-cells"



patternProperties:

  '-[0-9]+$':

    type: object

    additionalProperties: false

    patternProperties:

      'pins':

        type: object

        additionalProperties: false

        description: |

          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and input

          schmitt.

        $ref: "/schemas/pinctrl/pincfg-node.yaml"



        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in <soc>-pinfunc.h directly.



          bias-disable: true



          bias-pull-up:

            description: |

              Besides generic pinconfig options, it can be used as the pull up

              settings for 2 pull resistors, R0 and R1. User can configure those

              special pins. Some macros have been defined for this usage, such

              as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for

              valid arguments.



          bias-pull-down: true



          input-enable: true



          input-disable: true



          output-low: true



          output-high: true



          input-schmitt-enable: true



          input-schmitt-disable: true



          drive-strength:

            description: |

              Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,

              etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.



        required:

          - pinmux



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/pinctrl/mt8135-pinfunc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        syscfg_pctl_a: syscfg-pctl-a@10005000 {

          compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";

          reg = <0 0x10005000 0 0x1000>;

        };



        syscfg_pctl_b: syscfg-pctl-b@1020c020 {

          compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";

          reg = <0 0x1020C020 0 0x1000>;

        };



        pinctrl@1c20800 {

          compatible = "mediatek,mt8135-pinctrl";

          reg = <0 0x1000B000 0 0x1000>;

          mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;

          pins-are-numbered;

          gpio-controller;

          #gpio-cells = <2>;

          interrupt-controller;

          #interrupt-cells = <2>;

          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;



          i2c0_pins_a: i2c0-0 {

            pins1 {

              pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,

                <MT8135_PIN_101_SCL0__FUNC_SCL0>;

              bias-disable;

            };

          };



          i2c1_pins_a: i2c1-0 {

            pins {

              pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,

                <MT8135_PIN_196_SCL1__FUNC_SCL1>;

              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;

            };

          };



          i2c2_pins_a: i2c2-0 {

            pins1 {

              pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;

              bias-pull-down;

            };



            pins2 {

              pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;

              bias-pull-up;

            };

          };



          i2c3_pins_a: i2c3-0 {

            pins1 {

              pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,

                <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;

              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;

            };



            pins2 {

              pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,

                <MT8135_PIN_36_SDA3__FUNC_SDA3>;

              output-low;

              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;

            };



            pins3 {

              pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,

                <MT8135_PIN_60_JTDI__FUNC_JTDI>;

              drive-strength = <32>;

            };

          };

        };

    };