Commit 75d6e7d9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk updates from Stephen Boyd:
 "Nothing changed in the clk framework core this time around. We did get
  some updates to the basic clk types to use determine_rate for the
  divider type and add a power of two fractional divider flag though.

  Otherwise, this is a collection of clk driver updates. More than half
  the diffstat is in the Qualcomm clk driver where we add a bunch of
  data to describe clks on various SoCs and fix bugs. The other big new
  thing in here is the Mediatek MT8192 clk driver. That's been under
  review for a while and it's nice to see that it's finally upstream.

  Beyond that it's the usual set of minor fixes and tweaks to clk
  drivers. There are some non-clk driver bits in here which have all
  been acked by the respective maintainers.

  New Drivers:
   - Support video, gpu, display clks on qcom sc7280 SoCs
   - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
   - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
   - RPMh clks on qcom SM6350 SoCs
   - Support for Mediatek MT8192 SoCs
   - Add display (DU and DSI) clocks on Renesas R-Car V3U
   - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
     resets on Renesas RZ/G2L

  Updates:
   - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
   - Add power of two flag to fractional divider clk type
   - Migrate some clk drivers to clk_divider_ops.determine_rate
   - Migrate to clk_parent_data in gcc-sdm660
   - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
   - Switch from .round_rate to .determine_rate in clk-divider-gate
   - Fix clock tree update for TF-A controlled clocks for all i.MX8M
   - Add missing M7 core clock for i.MX8MN
   - YAML conversion of rk3399 clock controller binding
   - Removal of GRF dependency for the rk3328/rk3036 pll types
   - Drop CLK_IS_CRITICAL flag from Tegra fuse clk
   - Make CLK_R9A06G032 Kconfig symbol invisible
   - Convert various DT bindings to YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
  dt-bindings: clock: samsung: fix header path in example
  clk: tegra: fix old-style declaration
  clk: qcom: Add SM6350 GCC driver
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: clk-generated: Limit the requested rate to our range
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type
  ...
parents a180eab0 47505bf3

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required Properties: 
	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"

	- "mediatek,mt8167-audiosys", "syscon"

	- "mediatek,mt8183-audiosys", "syscon"

	- "mediatek,mt8192-audsys", "syscon"

	- "mediatek,mt8516-audsys", "syscon"

- #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ properties: 
              - mediatek,mt8167-mmsys

              - mediatek,mt8173-mmsys

              - mediatek,mt8183-mmsys

              - mediatek,mt8192-mmsys

              - mediatek,mt8365-mmsys

          - const: syscon

      - items:

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml

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+199 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Functional Clock Controller for MT8192



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The Mediatek functional clock controller provides various clocks on MT8192.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8192-scp_adsp

          - mediatek,mt8192-imp_iic_wrap_c

          - mediatek,mt8192-imp_iic_wrap_e

          - mediatek,mt8192-imp_iic_wrap_s

          - mediatek,mt8192-imp_iic_wrap_ws

          - mediatek,mt8192-imp_iic_wrap_w

          - mediatek,mt8192-imp_iic_wrap_n

          - mediatek,mt8192-msdc_top

          - mediatek,mt8192-msdc

          - mediatek,mt8192-mfgcfg

          - mediatek,mt8192-imgsys

          - mediatek,mt8192-imgsys2

          - mediatek,mt8192-vdecsys_soc

          - mediatek,mt8192-vdecsys

          - mediatek,mt8192-vencsys

          - mediatek,mt8192-camsys

          - mediatek,mt8192-camsys_rawa

          - mediatek,mt8192-camsys_rawb

          - mediatek,mt8192-camsys_rawc

          - mediatek,mt8192-ipesys

          - mediatek,mt8192-mdpsys



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    scp_adsp: clock-controller@10720000 {

        compatible = "mediatek,mt8192-scp_adsp";

        reg = <0x10720000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_c: clock-controller@11007000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_c";

        reg = <0x11007000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_e: clock-controller@11cb1000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_e";

        reg = <0x11cb1000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_s: clock-controller@11d03000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_s";

        reg = <0x11d03000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_ws: clock-controller@11d23000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_ws";

        reg = <0x11d23000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_w: clock-controller@11e01000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_w";

        reg = <0x11e01000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_n: clock-controller@11f02000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_n";

        reg = <0x11f02000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    msdc_top: clock-controller@11f10000 {

        compatible = "mediatek,mt8192-msdc_top";

        reg = <0x11f10000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    msdc: clock-controller@11f60000 {

        compatible = "mediatek,mt8192-msdc";

        reg = <0x11f60000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    mfgcfg: clock-controller@13fbf000 {

        compatible = "mediatek,mt8192-mfgcfg";

        reg = <0x13fbf000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys: clock-controller@15020000 {

        compatible = "mediatek,mt8192-imgsys";

        reg = <0x15020000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys2: clock-controller@15820000 {

        compatible = "mediatek,mt8192-imgsys2";

        reg = <0x15820000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys_soc: clock-controller@1600f000 {

        compatible = "mediatek,mt8192-vdecsys_soc";

        reg = <0x1600f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys: clock-controller@1602f000 {

        compatible = "mediatek,mt8192-vdecsys";

        reg = <0x1602f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vencsys: clock-controller@17000000 {

        compatible = "mediatek,mt8192-vencsys";

        reg = <0x17000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys: clock-controller@1a000000 {

        compatible = "mediatek,mt8192-camsys";

        reg = <0x1a000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawa: clock-controller@1a04f000 {

        compatible = "mediatek,mt8192-camsys_rawa";

        reg = <0x1a04f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawb: clock-controller@1a06f000 {

        compatible = "mediatek,mt8192-camsys_rawb";

        reg = <0x1a06f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawc: clock-controller@1a08f000 {

        compatible = "mediatek,mt8192-camsys_rawc";

        reg = <0x1a08f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    ipesys: clock-controller@1b000000 {

        compatible = "mediatek,mt8192-ipesys";

        reg = <0x1b000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    mdpsys: clock-controller@1f000000 {

        compatible = "mediatek,mt8192-mdpsys";

        reg = <0x1f000000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml

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+65 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek System Clock Controller for MT8192



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The Mediatek system clock controller provides various clocks and system configuration

  like reset and bus protection on MT8192.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8192-topckgen

          - mediatek,mt8192-infracfg

          - mediatek,mt8192-pericfg

          - mediatek,mt8192-apmixedsys

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    topckgen: syscon@10000000 {

        compatible = "mediatek,mt8192-topckgen", "syscon";

        reg = <0x10000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    infracfg: syscon@10001000 {

        compatible = "mediatek,mt8192-infracfg", "syscon";

        reg = <0x10001000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    pericfg: syscon@10003000 {

        compatible = "mediatek,mt8192-pericfg", "syscon";

        reg = <0x10003000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    apmixedsys: syscon@1000c000 {

        compatible = "mediatek,mt8192-apmixedsys", "syscon";

        reg = <0x1000c000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

+25 −2
Original line number Diff line number Diff line
@@ -61,13 +61,30 @@ properties: 
    maxItems: 1



  '#clock-cells':

    const: 1

    true



  clock-output-names:

    minItems: 1

    maxItems: 45



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - brcm,cygnus-armpll

              - brcm,nsp-armpll

    then:

      properties:

        '#clock-cells':

          const: 0

    else:

      properties:

        '#clock-cells':

          const: 1

      required:

        - clock-output-names

  - if:

      properties:

        compatible:
@@ -358,7 +375,6 @@ required: 
  - reg

  - clocks

  - '#clock-cells'

  - clock-output-names



additionalProperties: false
@@ -392,3 +408,10 @@ examples: 
        clocks = <&osc2>;

        clock-output-names = "keypad", "adc/touch", "pwm";

    };

  - |

    arm_clk@0 {

        #clock-cells = <0>;

        compatible = "brcm,nsp-armpll";

        clocks = <&osc>;

        reg = <0x0 0x1000>;

    };