Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next (47505bf3) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

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		@@ -61,13 +61,30 @@ properties:
		maxItems: 1

		'#clock-cells':
		const: 1
		true

		clock-output-names:
		minItems: 1
		maxItems: 45

		allOf:
		- if:
		properties:
		compatible:
		contains:
		enum:
		- brcm,cygnus-armpll
		- brcm,nsp-armpll
		then:
		properties:
		'#clock-cells':
		const: 0
		else:
		properties:
		'#clock-cells':
		const: 1
		required:
		- clock-output-names
		- if:
		properties:
		compatible:
		@@ -358,7 +375,6 @@ required:
		- reg
		- clocks
		- '#clock-cells'
		- clock-output-names

		additionalProperties: false

		@@ -392,3 +408,10 @@ examples:
		clocks = <&osc2>;
		clock-output-names = "keypad", "adc/touch", "pwm";
		};
		- \|
		arm_clk@0 {
		#clock-cells = <0>;
		compatible = "brcm,nsp-armpll";
		clocks = <&osc>;
		reg = <0x0 0x1000>;
		};

Documentation/devicetree/bindings/clock/clk-exynos-audss.txt

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		* Samsung Audio Subsystem Clock Controller

		The Samsung Audio Subsystem clock controller generates and supplies clocks
		to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
		binding described here is applicable to all SoCs in Exynos family.

		Required Properties:

		- compatible: should be one of the following:
		- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
		- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
		SoCs.
		- "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
		SoCs.
		- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
		SoCs.
		- reg: physical base address and length of the controller's register set.

		- #clock-cells: should be 1.

		- clocks:
		- pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
		is used if not specified.
		- pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
		is used if not specified.
		- cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
		specified.
		- sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
		not specified.
		- sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
		specified.

		- clock-names: Aliases for the above clocks. They should be "pll_ref",
		"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.

		Optional Properties:

		- power-domains: a phandle to respective power domain node as described by
		generic PM domain bindings (see power/power_domain.txt for more
		information).

		The following is the list of clocks generated by the controller. Each clock is
		assigned an identifier and client nodes use this identifier to specify the
		clock which they consume. Some of the clocks are available only on a particular
		Exynos4 SoC and this is specified where applicable.

		Provided clocks:

		Clock ID SoC (if specific)
		-----------------------------------------------

		mout_audss 0
		mout_i2s 1
		dout_srp 2
		dout_aud_bus 3
		dout_i2s 4
		srp_clk 5
		i2s_bus 6
		sclk_i2s 7
		pcm_bus 8
		sclk_pcm 9
		adma 10 Exynos5420

		Example 1: An example of a clock controller node using the default input
		clock names is listed below.

		clock_audss: audss-clock-controller@3810000 {
		compatible = "samsung,exynos5250-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		};

		Example 2: An example of a clock controller node with the input clocks
		specified.

		clock_audss: audss-clock-controller@3810000 {
		compatible = "samsung,exynos5250-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
		<&ext_i2s_clk>;
		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
		};

		Example 3: I2S controller node that consumes the clock generated by the clock
		controller. Refer to the standard clock bindings for information
		about 'clocks' and 'clock-names' property.

		i2s0: i2s@3830000 {
		compatible = "samsung,i2s-v5";
		reg = <0x03830000 0x100>;
		dmas = <&pdma0 10
		&pdma0 9
		&pdma0 8>;
		dma-names = "tx", "rx", "tx-sec";
		clocks = <&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_SCLK_I2S>,
		<&clock_audss EXYNOS_MOUT_AUDSS>,
		<&clock_audss EXYNOS_MOUT_I2S>;
		clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
		"mout_audss", "mout_i2s";
		};

Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt

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		* Samsung Audio Subsystem Clock Controller

		The Samsung Audio Subsystem clock controller generates and supplies clocks
		to Audio Subsystem block available in the S5PV210 and compatible SoCs.

		Required Properties:

		- compatible: should be "samsung,s5pv210-audss-clock".
		- reg: physical base address and length of the controller's register set.

		- #clock-cells: should be 1.

		- clocks:
		- hclk: AHB bus clock of the Audio Subsystem.
		- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
		not specified (i.e. xusbxti is used for PLL reference), it is fixed to
		a clock named "xxti".
		- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
		- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
		specified, it is fixed to a clock named "iiscdclk0".
		- sclk_audio0: Audio bus clock, parent of mout_i2s.

		- clock-names: Aliases for the above clocks. They should be "hclk",
		"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
		tree sources.

		Example: Clock controller node.

		clk_audss: clock-controller@c0900000 {
		compatible = "samsung,s5pv210-audss-clock";
		reg = <0xc0900000 0x1000>;
		#clock-cells = <1>;
		clock-names = "hclk", "xxti",
		"fout_epll", "sclk_audio0";
		clocks = <&clocks DOUT_HCLKP>, <&xxti>,
		<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
		};

		Example: I2S controller node that consumes the clock generated by the clock
		controller. Refer to the standard clock bindings for information
		about 'clocks' and 'clock-names' property.

		i2s0: i2s@3830000 {
		/* ... */
		clock-names = "iis", "i2s_opclk0",
		"i2s_opclk1";
		clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
		<&clk_audss CLK_DOUT_AUD_BUS>;
		/* ... */
		};

Documentation/devicetree/bindings/clock/exynos3250-clock.txt

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		* Samsung Exynos3250 Clock Controller

		The Exynos3250 clock controller generates and supplies clock to various
		controllers within the Exynos3250 SoC.

		Required Properties:

		- compatible: should be one of the following.
		- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
		- "samsung,exynos3250-cmu-dmc" - controller compatible with
		Exynos3250 SoC for Dynamic Memory Controller domain.
		- "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
		with Exynos3250 SOC

		- reg: physical base address of the controller and length of memory mapped
		region.

		- #clock-cells: should be 1.

		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos3250.h header and can be used in device
		tree sources.

		Example 1: Examples of clock controller nodes are listed below.

		cmu: clock-controller@10030000 {
		compatible = "samsung,exynos3250-cmu";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
		};

		cmu_dmc: clock-controller@105c0000 {
		compatible = "samsung,exynos3250-cmu-dmc";
		reg = <0x105C0000 0x2000>;
		#clock-cells = <1>;
		};

		cmu_isp: clock-controller@10048000 {
		compatible = "samsung,exynos3250-cmu-isp";
		reg = <0x10048000 0x1000>;
		#clock-cells = <1>;
		};

		Example 2: UART controller node that consumes the clock generated by the clock
		controller. Refer to the standard clock bindings for information
		about 'clocks' and 'clock-names' property.

		serial@13800000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13800000 0x100>;
		interrupts = <0 109 0>;
		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
		clock-names = "uart", "clk_uart_baud0";
		};

Documentation/devicetree/bindings/clock/exynos4-clock.txt

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		* Samsung Exynos4 Clock Controller

		The Exynos4 clock controller generates and supplies clock to various controllers
		within the Exynos4 SoC. The clock binding described here is applicable to all
		SoC's in the Exynos4 family.

		Required Properties:

		- compatible: should be one of the following.
		- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
		- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.

		- reg: physical base address of the controller and length of memory mapped
		region.

		- #clock-cells: should be 1.

		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos4.h header and can be used in device
		tree sources.

		Example 1: An example of a clock controller node is listed below.

		clock: clock-controller@10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
		};

		Example 2: UART controller node that consumes the clock generated by the clock
		controller. Refer to the standard clock bindings for information
		about 'clocks' and 'clock-names' property.

		serial@13820000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
		};

		Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
		subsystem. Registers for those clocks are located in the ISP power domain.
		Because those registers are also located in a different memory region than
		the main clock controller, a separate clock controller has to be defined for
		handling them.

		Required Properties:

		- compatible: should be "samsung,exynos4412-isp-clock".

		- reg: physical base address of the ISP clock controller and length of memory
		mapped region.

		- #clock-cells: should be 1.

		- clocks: list of the clock controller input clock identifiers,
		from common clock bindings, should point to CLK_ACLK200 and
		CLK_ACLK400_MCUISP clocks from the main clock controller.

		- clock-names: list of the clock controller input clock names,
		as described in clock-bindings.txt, should be "aclk200" and
		"aclk400_mcuisp".

		- power-domains: a phandle to ISP power domain node as described by
		generic PM domain bindings.

		Example 3: The clock controllers bindings for Exynos4412 SoCs.

		clock: clock-controller@10030000 {
		compatible = "samsung,exynos4412-clock";
		reg = <0x10030000 0x18000>;
		#clock-cells = <1>;
		};

		isp_clock: clock-controller@10048000 {
		compatible = "samsung,exynos4412-isp-clock";
		reg = <0x10048000 0x1000>;
		#clock-cells = <1>;
		power-domains = <&pd_isp>;
		clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
		clock-names = "aclk200", "aclk400_mcuisp";
		};