Commit 8fb59ce1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5' into clk-next 

 - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators

* clk-nvidia:
  clk: tegra: fix old-style declaration
  clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>

* clk-rockchip:
  clk: rockchip: make rk3308 ddrphy4x clock critical
  clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
  dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
  clk: rockchip: Add support for hclk_sfc on rk3036
  clk: rockchip: rk3036: fix up the sclk_sfc parent error
  clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036

* clk-at91:
  clk: at91: clk-generated: Limit the requested rate to our range

* clk-vc5:
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
parents 1faa7cb2 27115441 1d070108 af7651e6 d83e561d

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

+40 −0
Original line number Diff line number Diff line
@@ -30,6 +30,20 @@ description: | 
    3 -- OUT3

    4 -- OUT4



  The idt,shutdown and idt,output-enable-active properties control the

  SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown

  Register, respectively. Their behavior is summarized by the following

  table:



  SH SP Output when the SD/OE pin is Low/High

  == == =====================================

   0  0 Active/Inactive

   0  1 Inactive/Active

   1  0 Active/Shutdown

   1  1 Inactive/Shutdown



  The case where SH and SP are both 1 is likely not very interesting.



maintainers:

  - Luca Ceresoli <luca@lucaceresoli.net>
@@ -64,6 +78,26 @@ properties: 
    maximum: 22760

    description: Optional load capacitor for XTAL1 and XTAL2



  idt,shutdown:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      If 1, this enables the shutdown functionality: the chip will be

      shut down if the SD/OE pin is driven high. If 0, this disables the

      shutdown functionality: the chip will never be shut down based on

      the value of the SD/OE pin. This property corresponds to the SH

      bit of the Primary Source and Shutdown Register.



  idt,output-enable-active:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      If 1, this enables output when the SD/OE pin is high, and disables

      output when the SD/OE pin is low. If 0, this disables output when

      the SD/OE pin is high, and enables output when the SD/OE pin is

      low. This corresponds to the SP bit of the Primary Source and

      Shutdown Register.



patternProperties:

  "^OUT[1-4]$":

    type: object
@@ -90,6 +124,8 @@ required: 
  - compatible

  - reg

  - '#clock-cells'

  - idt,shutdown

  - idt,output-enable-active



allOf:

  - if:
@@ -139,6 +175,10 @@ examples: 
            clocks = <&ref25m>;

            clock-names = "xin";



            /* Set the SD/OE pin's settings */

            idt,shutdown = <0>;

            idt,output-enable-active = <0>;



            OUT1 {

                idt,mode = <VC5_CMOSD>;

                idt,voltage-microvolt = <1800000>;

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

deleted100644 → 0
+0 −68
Original line number Diff line number Diff line 
* Rockchip RK3399 Clock and Reset Unit



The RK3399 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"

- compatible: CRU should be "rockchip,rk3399-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files".

  It is used for GRF muxes, if missing any muxes present in the GRF will not

  be available.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "clkin_gmac" - external GMAC clock - optional,

 - "clkin_i2s" - external I2S clock - optional,

 - "pclkin_cif" - external ISP clock - optional,

 - "clk_usbphy0_480m" - output clock of the pll in the usbphy0

 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1



Example: Clock controller node:



	pmucru: pmu-clock-controller@ff750000 {

		compatible = "rockchip,rk3399-pmucru";

		reg = <0x0 0xff750000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	cru: clock-controller@ff760000 {

		compatible = "rockchip,rk3399-cru";

		reg = <0x0 0xff760000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff1a0000 {

		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff180000 0x0 0x100>;

		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;

		clock-names = "baudclk", "apb_pclk";

		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

	};

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml

0 → 100644
+92 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3399 Clock and Reset Unit



maintainers:

  - Xing Zheng <zhengxing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The RK3399 clock controller generates and supplies clock to various

  controllers within the SoC and also implements a reset controller for SoC

  peripherals.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be

  used in device tree sources. Similar macros exist for the reset sources in

  these files.

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names:

    - "xin24m" - crystal input - required,

    - "xin32k" - rtc clock - optional,

    - "clkin_gmac" - external GMAC clock - optional,

    - "clkin_i2s" - external I2S clock - optional,

    - "pclkin_cif" - external ISP clock - optional,

    - "clk_usbphy0_480m" - output clock of the pll in the usbphy0

    - "clk_usbphy1_480m" - output clock of the pll in the usbphy1



properties:

  compatible:

    enum:

      - rockchip,rk3399-pmucru

      - rockchip,rk3399-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 1



  assigned-clocks:

    minItems: 1

    maxItems: 64



  assigned-clock-parents:

    minItems: 1

    maxItems: 64



  assigned-clock-rates:

    minItems: 1

    maxItems: 64



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: >

      phandle to the syscon managing the "general register files". It is used

      for GRF muxes, if missing any muxes present in the GRF will not be

      available.



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    pmucru: pmu-clock-controller@ff750000 {

      compatible = "rockchip,rk3399-pmucru";

      reg = <0xff750000 0x1000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

  - |

    cru: clock-controller@ff760000 {

      compatible = "rockchip,rk3399-cru";

      reg = <0xff760000 0x1000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

arch/arm/mach-tegra/pm.c

+1 −1
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ static const struct platform_suspend_ops tegra_suspend_ops = { 
	.enter		= tegra_suspend_enter,

};



void __init tegra_init_suspend(void)

void tegra_pm_init_suspend(void)

{

	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

arch/arm/mach-tegra/pm.h

+0 −6
Original line number Diff line number Diff line
@@ -25,10 +25,4 @@ void tegra30_sleep_core_init(void); 


extern void (*tegra_tear_down_cpu)(void);



#ifdef CONFIG_PM_SLEEP

void tegra_init_suspend(void);

#else

static inline void tegra_init_suspend(void) {}

#endif



#endif /* _MACH_TEGRA_PM_H_ */