Commit c76c1a42 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Include headers for PWR and SMUIO registers 



Clean up the smu10, smu12, and gfx9 drivers to use headers for
registers instead of hardcoding in the C source files.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c8e42d57

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −7
Original line number Diff line number Diff line
@@ -50,18 +50,14 @@ 


#include "gfx_v9_4.h"



#include "asic_reg/pwr/pwr_10_0_offset.h"

#include "asic_reg/pwr/pwr_10_0_sh_mask.h"



#define GFX9_NUM_GFX_RINGS     1

#define GFX9_MEC_HPD_SIZE 4096

#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L

#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L



#define mmPWR_MISC_CNTL_STATUS					0x0183

#define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT	0x0

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT		0x1

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L



#define mmGCEA_PROBE_MAP                        0x070c

#define mmGCEA_PROBE_MAP_BASE_IDX               0

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+2 −7
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 
#include "power_state.h"

#include "soc15_common.h"

#include "smu10.h"

#include "asic_reg/pwr/pwr_10_0_offset.h"

#include "asic_reg/pwr/pwr_10_0_sh_mask.h"



#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5

#define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
@@ -43,13 +45,6 @@ 
#define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */

#define SMC_RAM_END                     0x40000



#define mmPWR_MISC_CNTL_STATUS					0x0183

#define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT	0x0

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT		0x1

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L



static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;

drivers/gpu/drm/amd/powerplay/smu_v12_0.c

+7 −5
Original line number Diff line number Diff line
@@ -32,13 +32,15 @@ 


#include "asic_reg/mp/mp_12_0_0_offset.h"

#include "asic_reg/mp/mp_12_0_0_sh_mask.h"

#include "asic_reg/smuio/smuio_12_0_0_offset.h"

#include "asic_reg/smuio/smuio_12_0_0_sh_mask.h"



#define smnMP1_FIRMWARE_FLAGS                                0x3010024

// because some SMU12 based ASICs use older ip offset tables

// we should undefine this register from the smuio12 header

// to prevent confusion down the road

#undef mmPWR_MISC_CNTL_STATUS



#define mmSMUIO_GFX_MISC_CNTL                                0x00c8

#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                       0

#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK          0x00000006L

#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT        0x1

#define smnMP1_FIRMWARE_FLAGS                                0x3010024



int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,

					      uint16_t msg)