Commit c8e42d57 authored by xinhui pan's avatar xinhui pan Committed by Alex Deucher
Browse files

drm/amdgpu: implement more ib pools (v2) 



We have three ib pools, they are normal, VM, direct pools.

Any jobs which schedule IBs without dependence on gpu scheduler should
use DIRECT pool.

Any jobs schedule direct VM update IBs should use VM pool.

Any other jobs use NORMAL pool.

v2: squash in coding style fix

Signed-off-by: default avatarxinhui pan <xinhui.pan@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac60b229

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+11 −2
Original line number Diff line number Diff line
@@ -388,6 +388,13 @@ struct amdgpu_sa_bo { 
int amdgpu_fence_slab_init(void);

void amdgpu_fence_slab_fini(void);



enum amdgpu_ib_pool_type {

	AMDGPU_IB_POOL_NORMAL = 0,

	AMDGPU_IB_POOL_VM,

	AMDGPU_IB_POOL_DIRECT,



	AMDGPU_IB_POOL_MAX

};

/*

 * IRQS.

 */
@@ -439,7 +446,9 @@ struct amdgpu_fpriv { 
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib);

		  unsigned size,

		  enum amdgpu_ib_pool_type pool,

		  struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
@@ -843,7 +852,7 @@ struct amdgpu_device { 
	unsigned			num_rings;

	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];

	bool				ib_pool_ready;

	struct amdgpu_sa_manager	ring_tmp_bo;

	struct amdgpu_sa_manager	ring_tmp_bo[AMDGPU_IB_POOL_MAX];



	/* interrupts */

	struct amdgpu_irq		irq;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -924,7 +924,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 


		ring = to_amdgpu_ring(entity->rq->sched);

		r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?

				   chunk_ib->ib_bytes : 0, ib);

				   chunk_ib->ib_bytes : 0, AMDGPU_IB_POOL_NORMAL, ib);

		if (r) {

			DRM_ERROR("Failed to get ib !\n");

			return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+30 −12
Original line number Diff line number Diff line
@@ -61,12 +61,14 @@ 
 * Returns 0 on success, error on failure.

 */

int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib)

		unsigned size,

		enum amdgpu_ib_pool_type pool_type,

		struct amdgpu_ib *ib)

{

	int r;



	if (size) {

		r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,

		r = amdgpu_sa_bo_new(&adev->ring_tmp_bo[pool_type],

				      &ib->sa_bo, size, 256);

		if (r) {

			dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
@@ -280,19 +282,27 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
 */

int amdgpu_ib_pool_init(struct amdgpu_device *adev)

{

	int r;

	int r, i;

	unsigned size;



	if (adev->ib_pool_ready) {

		return 0;

	}

	r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,

				      AMDGPU_IB_POOL_SIZE*64*1024,

	for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {

		if (i == AMDGPU_IB_POOL_DIRECT)

			size = PAGE_SIZE * 2;

		else

			size = AMDGPU_IB_POOL_SIZE*64*1024;

		r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo[i],

				size,

				AMDGPU_GPU_PAGE_SIZE,

				AMDGPU_GEM_DOMAIN_GTT);

		if (r) {

			for (i--; i >= 0; i--)

				amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo[i]);

			return r;

		}



	}

	adev->ib_pool_ready = true;



	return 0;
@@ -308,8 +318,11 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev) 
 */

void amdgpu_ib_pool_fini(struct amdgpu_device *adev)

{

	int i;



	if (adev->ib_pool_ready) {

		amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);

		for (i = 0; i < AMDGPU_IB_POOL_MAX; i++)

			amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo[i]);

		adev->ib_pool_ready = false;

	}

}
@@ -406,7 +419,12 @@ static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	struct amdgpu_device *adev = dev->dev_private;



	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);

	seq_printf(m, "-------------------- NORMAL -------------------- \n");

	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_NORMAL], m);

	seq_printf(m, "---------------------- VM ---------------------- \n");

	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_VM], m);

	seq_printf(m, "-------------------- DIRECT--------------------- \n");

	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_DIRECT], m);



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+3 −2
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 
}



int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

		enum amdgpu_ib_pool_type pool_type,

		struct amdgpu_job **job)

{

	int r;
@@ -95,7 +96,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 
	if (r)

		return r;



	r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);

	r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);

	if (r)

		kfree(*job);

drivers/gpu/drm/amd/amdgpu/amdgpu_job.h

+2 −2
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)



struct amdgpu_fence;

enum amdgpu_ib_pool_type;



struct amdgpu_job {

	struct drm_sched_job    base;
@@ -67,8 +68,7 @@ struct amdgpu_job { 
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



		enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);

void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,