Commit c75e416c authored by Daniel Golle's avatar Daniel Golle Committed by Jakub Kicinski
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net: ethernet: mtk_eth_soc: convert clock bitmap to u64 



The to-be-added MT7988 SoC adds many new clocks which need to be
controlled by the Ethernet driver, which will result in their total
number exceeding 32.
Prepare by converting clock bitmaps into 64-bit types.

Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 51a4df60

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+49 −47
Original line number Diff line number Diff line
@@ -666,54 +666,56 @@ enum mtk_clks_map { 
	MTK_CLK_MAX

};



#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_TRGPLL))

#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL))

#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_TRGPLL))

#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK) | \

				 BIT_ULL(MTK_CLK_ETH2PLL))

#define MT7621_CLKS_BITMAP	(0)

#define MT7628_CLKS_BITMAP	(0)

#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))

#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_WOCPU0) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK))

#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB))

#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK) | \

				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))

#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_WOCPU0) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK))

#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))



enum mtk_dev_state {

	MTK_HW_INIT,
@@ -1046,7 +1048,7 @@ struct mtk_soc_data { 
	const struct mtk_reg_map *reg_map;

	u32             ana_rgc3;

	u64		caps;

	u32		required_clks;

	u64		required_clks;

	bool		required_pctl;

	u8		offload_version;

	u8		hash_offset;