Commit c707b73f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.14-2021-06-09' of... 

Merge tag 'amd-drm-next-5.14-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-5.14-2021-06-09:

amdgpu:
- SR-IOV fixes
- Smartshift updates
- GPUVM TLB flush updates
- 16bpc fixed point display fix for DCE11
- BACO cleanups and core refactoring
- Aldebaran updates
- Initial Yellow Carp support
- RAS fixes
- PM API cleanup
- DC visual confirm updates
- DC DP MST fixes
- DC DML fixes
- Misc code cleanups and bug fixes

amdkfd:
- Initial Yellow Carp support

radeon:
- memcpy_to/from_io fixes

UAPI:
- Add Yellow Carp chip family id
  Used internally in the kernel driver and by mesa

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210610031649.4006-1-alexander.deucher@amd.com
parents a2098e85 2c1b1ac7

Documentation/gpu/amdgpu.rst

+21 −0
Original line number Diff line number Diff line
@@ -300,4 +300,25 @@ pcie_replay_count 
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: pcie_replay_count



+GPU SmartShift Information

============================



GPU SmartShift information via sysfs



smartshift_apu_power

--------------------



.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: smartshift_apu_power



smartshift_dgpu_power

---------------------



.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: smartshift_dgpu_power



smartshift_bias

---------------



.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: smartshift_bias

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ amdgpu-y += \ 
	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \

	beige_goby_reg_init.o

	beige_goby_reg_init.o yellow_carp_reg_init.o



# add DF block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+10 −0
Original line number Diff line number Diff line
@@ -211,6 +211,7 @@ extern int amdgpu_discovery; 
extern int amdgpu_mes;

extern int amdgpu_noretry;

extern int amdgpu_force_asic_type;

extern int amdgpu_smartshift_bias;

#ifdef CONFIG_HSA_AMD

extern int sched_policy;

extern bool debug_evictions;
@@ -268,6 +269,10 @@ extern int amdgpu_num_kcq; 
#define CIK_CURSOR_WIDTH 128

#define CIK_CURSOR_HEIGHT 128



/* smasrt shift bias level limits */

#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)

#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)



struct amdgpu_device;

struct amdgpu_ib;

struct amdgpu_cs_parser;
@@ -1280,6 +1285,11 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 
int amdgpu_device_baco_enter(struct drm_device *dev);

int amdgpu_device_baco_exit(struct drm_device *dev);



void amdgpu_device_flush_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring);

void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)

void amdgpu_register_atpx_handler(void);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+1 −1
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 
		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,

		uint64_t *size);

int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(

		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);

		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed);

int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(

		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);

int amdgpu_amdkfd_gpuvm_sync_memory(

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+21 −21
Original line number Diff line number Diff line
@@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid, 


	lock_srbm(kgd, 0, 0, 0, vmid);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);

	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);

	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);

	/* APE1 no longer exists on GFX9 */



	unlock_srbm(kgd);
@@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id) 


	lock_srbm(kgd, mec, pipe, 0, 0);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),

	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,

		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
@@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 


		pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",

			mec, pipe, queue_id);

		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));

		value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

			((mec << 5) | (pipe << 3) | queue_id | 0x80));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);

		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);

	}



	/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
@@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 


	for (reg = hqd_base;

	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

		WREG32(reg, mqd_hqd[reg - hqd_base]);

		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);





	/* Activate doorbell logic before triggering WPTR poll. */

	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);

	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);



	if (wptr) {

		/* Don't read wptr with get_user because the user
@@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 
		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);

		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;



		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,

		       lower_32_bits(guessed_wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

		       upper_32_bits(guessed_wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,

		       lower_32_bits((uint64_t)wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

		       upper_32_bits((uint64_t)wptr));

		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,

			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,

		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));

	}
@@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 
			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));



	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);

	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);



	release_queue(kgd);
@@ -350,7 +350,7 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd, 
		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\

			break;				\

		(*dump)[i][0] = (addr) << 2;		\

		(*dump)[i++][1] = RREG32(addr);		\

		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\

	} while (0)



	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -482,13 +482,13 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address, 
	uint32_t low, high;



	acquire_queue(kgd, pipe_id, queue_id);

	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

	if (act) {

		low = lower_32_bits(queue_address >> 8);

		high = upper_32_bits(queue_address >> 8);



		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&

		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))

		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

			retval = true;

	}

	release_queue(kgd);
@@ -542,11 +542,11 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd, 
		break;

	}



	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);

	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);



	end_jiffies = (utimeout * HZ / 1000) + jiffies;

	while (true) {

		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))

			break;

		if (time_after(jiffies, end_jiffies)) {
@@ -626,7 +626,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd, 


	mutex_lock(&adev->grbm_idx_mutex);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);



	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
@@ -636,7 +636,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd, 
	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

		SE_BROADCAST_WRITES, 1);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

	mutex_unlock(&adev->grbm_idx_mutex);



	return 0;