Commit c6e90a1c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.18-2022-03-18' of... 

Merge tag 'amd-drm-next-5.18-2022-03-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.18-2022-03-18:

amdgpu:
- Aldebaran fixes
- SMU 13.0.5 fixes
- DCN 3.1.5 fixes
- DCN 3.1.6 fixes
- Pipe split fixes
- More display FP cleanup
- DP 2.0 UHBR fix
- DC GPU reset fix
- DC deep color ratio fix
- SMU robustness fixes
- Runtime PM fix for APUs
- IGT reload fixes
- SR-IOV fix
- Misc fixes and cleanups

amdkfd:
- CRIU fixes
- SVM fixes

UAPI:
- Properly handle SDMA transfers with CRIU
  Proposed user mode change: https://github.com/checkpoint-restore/criu/pull/1709



Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220318203717.5833-1-alexander.deucher@amd.com
parents f11de861 426c89aa

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -53,11 +53,11 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \

	amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \

	amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \

	amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o \

	amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o \

	amdgpu_eeprom.o amdgpu_mca.o



amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

+2 −2
Original line number Diff line number Diff line
@@ -626,7 +626,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 
		if (mode->type & DRM_MODE_TYPE_PREFERRED) {

			if (mode->hdisplay != native_mode->hdisplay ||

			    mode->vdisplay != native_mode->vdisplay)

				memcpy(native_mode, mode, sizeof(*mode));

				drm_mode_copy(native_mode, mode);

		}

	}
@@ -635,7 +635,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 
		list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {

			if (mode->hdisplay == native_mode->hdisplay &&

			    mode->vdisplay == native_mode->vdisplay) {

				*native_mode = *mode;

				drm_mode_copy(native_mode, mode);

				drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);

				DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");

				break;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, 
	if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {

		s64 min_us;



		/* Be more aggresive on dGPUs. Try to fill a portion of free

		/* Be more aggressive on dGPUs. Try to fill a portion of free

		 * VRAM now.

		 */

		if (!(adev->flags & AMD_IS_APU))
@@ -1280,7 +1280,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
			continue;



		/*

		 * Work around dma_resv shortcommings by wrapping up the

		 * Work around dma_resv shortcomings by wrapping up the

		 * submission in a dma_fence_chain and add it as exclusive

		 * fence.

		 */

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+13 −11
Original line number Diff line number Diff line
@@ -2159,8 +2159,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
	    !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))

		adev->flags |= AMD_IS_PX;



	if (!(adev->flags & AMD_IS_APU)) {

		parent = pci_upstream_bridge(adev->pdev);

		adev->has_pr3 = parent ? pci_pr3_present(parent) : false;

	}



	amdgpu_amdkfd_device_probe(adev);
@@ -3664,6 +3666,15 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)

		adev->enable_mes = true;



	/*

	 * Reset domain needs to be present early, before XGMI hive discovered

	 * (if any) and intitialized to use reset sem and in_gpu reset flag

	 * early on during init and before calling to RREG32.

	 */

	adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");

	if (!adev->reset_domain)

		return -ENOMEM;



	/* detect hw virtualization here */

	amdgpu_detect_virtualization(adev);
@@ -3673,15 +3684,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
		return r;

	}



	/*

	 * Reset domain needs to be present early, before XGMI hive discovered

	 * (if any) and intitialized to use reset sem and in_gpu reset flag

	 * early on during init.

	 */

	adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE ,"amdgpu-reset-dev");

	if (!adev->reset_domain)

		return -ENOMEM;



	/* early init functions */

	r = amdgpu_device_ip_early_init(adev);

	if (r)

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+22 −19
Original line number Diff line number Diff line
@@ -622,6 +622,13 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 
{

	unsigned size;



	/*

	 * Some ASICs need to reserve a region of video memory to avoid access

	 * from driver

	 */

	adev->mman.stolen_reserved_offset = 0;

	adev->mman.stolen_reserved_size = 0;



	/*

	 * TODO:

	 * Currently there is a bug where some memory client outside
@@ -632,10 +639,25 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 
	 */

	switch (adev->asic_type) {

	case CHIP_VEGA10:

		adev->mman.keep_stolen_vga_memory = true;

		/*

		 * VEGA10 SRIOV VF needs some firmware reserved area.

		 */

		if (amdgpu_sriov_vf(adev)) {

			adev->mman.stolen_reserved_offset = 0x100000;

			adev->mman.stolen_reserved_size = 0x600000;

		}

		break;

	case CHIP_RAVEN:

	case CHIP_RENOIR:

		adev->mman.keep_stolen_vga_memory = true;

		break;

	case CHIP_YELLOW_CARP:

		if (amdgpu_discovery == 0) {

			adev->mman.stolen_reserved_offset = 0x1ffb0000;

			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;

		}

		break;

	default:

		adev->mman.keep_stolen_vga_memory = false;

		break;
@@ -756,25 +778,6 @@ uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo 
	return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;

}



void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev)

{

	/* Some ASICs need to reserve a region of video memory to avoid access

	 * from driver */

	adev->mman.stolen_reserved_offset = 0;

	adev->mman.stolen_reserved_size = 0;



	switch (adev->asic_type) {

	case CHIP_YELLOW_CARP:

		if (amdgpu_discovery == 0) {

			adev->mman.stolen_reserved_offset = 0x1ffb0000;

			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;

		}

		break;

	default:

		break;

	}

}



int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)

{

	struct amdgpu_bo *vram_bo = NULL;