Commit c501cf9c authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/mediatek' 

- Split DT bindings for PCIe controllers with independent MSI domains into
  separate nodes for MT2712/MT7622 (Chuanjia Liu)

- Locate shared registers from "mediatek,generic-pciecfg" property
  (Chuanjia Liu)

- Get IRQ from "pcie_irq" if "interrupt-names" property is present to fix
  an MSI issue (Chuanjia Liu)

- Get PCI domain from "linux,pci-domain" property if present (Chuanjia Liu)

* remotes/lorenzo/pci/mediatek:
  PCI: mediatek: Use PCI domain to handle ports detection
  PCI: mediatek: Add new method to get irq number
  PCI: mediatek: Add new method to get shared pcie-cfg base address
  dt-bindings: PCI: mediatek: Update the Device tree bindings
parents af42a0d4 77216702

Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml

0 → 100644
+39 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek PCIECFG controller



maintainers:

  - Chuanjia Liu <chuanjia.liu@mediatek.com>

  - Jianjun Wang <jianjun.wang@mediatek.com>



description: |

  The MediaTek PCIECFG controller controls some feature about

  LTSSM, ASPM and so on.



properties:

  compatible:

    items:

      - enum:

          - mediatek,generic-pciecfg

      - const: syscon



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    pciecfg: pciecfg@1a140000 {

        compatible = "mediatek,generic-pciecfg", "syscon";

        reg = <0x1a140000 0x1000>;

    };

...

Documentation/devicetree/bindings/pci/mediatek-pcie.txt

+111 −95
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ Required properties: 
	"mediatek,mt7623-pcie"

	"mediatek,mt7629-pcie"

- device_type: Must be "pci"

- reg: Base addresses and lengths of the PCIe subsys and root ports.

- reg: Base addresses and lengths of the root ports.

- reg-names: Names of the above areas to use during resource lookup.

- #address-cells: Address representation for root ports (must be 3)

- #size-cells: Size representation for root ports (must be 2)
@@ -47,9 +47,12 @@ Required properties for MT7623/MT2701: 
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the

  number of root ports.



Required properties for MT2712/MT7622:

Required properties for MT2712/MT7622/MT7629:

-interrupts: A list of interrupt outputs of the controller, must have one

	     entry for each PCIe port

- interrupt-names: Must include the following entries:

	- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received

- linux,pci-domain: PCI domain ID. Should be unique for each host controller



In addition, the device tree node must have sub-nodes describing each

PCIe port interface, having the following mandatory properties:
@@ -143,103 +146,97 @@ Examples for MT7623: 


Examples for MT2712:



	pcie: pcie@11700000 {

	pcie1: pcie@112ff000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x11700000 0 0x1000>,

		      <0 0x112ff000 0 0x1000>;

		reg-names = "port0", "port1";

		reg = <0 0x112ff000 0 0x1000>;

		reg-names = "port1";

		linux,pci-domain = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE0>,

		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE1>;

		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1";

		clock-names = "sys_ck1", "ahb_ck1";

		phys = <&u3port1 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy1";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;

		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;

		status = "disabled";



		pcie0: pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc0 0>,

					<0 0 0 2 &pcie_intc0 1>,

					<0 0 0 3 &pcie_intc0 2>,

					<0 0 0 4 &pcie_intc0 3>;

			pcie_intc0: interrupt-controller {

		interrupt-map = <0 0 0 1 &pcie_intc1 0>,

				<0 0 0 2 &pcie_intc1 1>,

				<0 0 0 3 &pcie_intc1 2>,

				<0 0 0 4 &pcie_intc1 3>;

		pcie_intc1: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



		pcie1: pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

	pcie0: pcie@11700000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x11700000 0 0x1000>;

		reg-names = "port0";

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&pericfg CLK_PERI_PCIE0>;

		clock-names = "sys_ck0", "ahb_ck0";

		phys = <&u3port0 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;

		status = "disabled";



		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc1 0>,

					<0 0 0 2 &pcie_intc1 1>,

					<0 0 0 3 &pcie_intc1 2>,

					<0 0 0 4 &pcie_intc1 3>;

			pcie_intc1: interrupt-controller {

		interrupt-map = <0 0 0 1 &pcie_intc0 0>,

				<0 0 0 2 &pcie_intc0 1>,

				<0 0 0 3 &pcie_intc0 2>,

				<0 0 0 4 &pcie_intc0 3>;

		pcie_intc0: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};

	};



Examples for MT7622:



	pcie: pcie@1a140000 {

	pcie0: pcie@1a143000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>,

		      <0 0x1a143000 0 0x1000>,

		      <0 0x1a145000 0 0x1000>;

		reg-names = "subsys", "port0", "port1";

		reg = <0 0x1a143000 0 0x1000>;

		reg-names = "port0";

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;

		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "pcie_irq";

		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,

			 <&pciesys CLK_PCIE_P1_MAC_EN>,

			 <&pciesys CLK_PCIE_P0_AHB_EN>,

			 <&pciesys CLK_PCIE_P1_AHB_EN>,

			 <&pciesys CLK_PCIE_P0_AUX_EN>,

			 <&pciesys CLK_PCIE_P1_AUX_EN>,

			 <&pciesys CLK_PCIE_P0_AXI_EN>,

			 <&pciesys CLK_PCIE_P1_AXI_EN>,

			 <&pciesys CLK_PCIE_P0_OBFF_EN>,

			 <&pciesys CLK_PCIE_P1_OBFF_EN>,

			 <&pciesys CLK_PCIE_P0_PIPE_EN>,

			 <&pciesys CLK_PCIE_P1_PIPE_EN>;

		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",

			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",

			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1";

			 <&pciesys CLK_PCIE_P0_PIPE_EN>;

		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",

			      "axi_ck0", "obff_ck0", "pipe_ck0";



		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;

		status = "disabled";



		pcie0: pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc0 0>,

				<0 0 0 2 &pcie_intc0 1>,
@@ -252,12 +249,32 @@ Examples for MT7622: 
		};

	};



		pcie1: pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

	pcie1: pcie@1a145000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";

		reg = <0 0x1a145000 0 0x1000>;

		reg-names = "port1";

		linux,pci-domain = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "pcie_irq";

		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,

			 /* designer has connect RC1 with p0_ahb clock */

			 <&pciesys CLK_PCIE_P0_AHB_EN>,

			 <&pciesys CLK_PCIE_P1_AUX_EN>,

			 <&pciesys CLK_PCIE_P1_AXI_EN>,

			 <&pciesys CLK_PCIE_P1_OBFF_EN>,

			 <&pciesys CLK_PCIE_P1_PIPE_EN>;

		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",

			      "axi_ck1", "obff_ck1", "pipe_ck1";



		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;

		status = "disabled";



		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc1 0>,

				<0 0 0 2 &pcie_intc1 1>,
@@ -269,4 +286,3 @@ Examples for MT7622: 
			#interrupt-cells = <1>;

		};

	};
 
	};

drivers/pci/controller/pcie-mediatek.c

+39 −13
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/msi.h>

#include <linux/module.h>

#include <linux/of_address.h>
@@ -23,6 +24,7 @@ 
#include <linux/phy/phy.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/regmap.h>

#include <linux/reset.h>



#include "../pci.h"
@@ -207,6 +209,7 @@ struct mtk_pcie_port { 
 * struct mtk_pcie - PCIe host information

 * @dev: pointer to PCIe device

 * @base: IO mapped register base

 * @cfg: IO mapped register map for PCIe config

 * @free_ck: free-run reference clock

 * @mem: non-prefetchable memory resource

 * @ports: pointer to PCIe port information
@@ -215,6 +218,7 @@ struct mtk_pcie_port { 
struct mtk_pcie {

	struct device *dev;

	void __iomem *base;

	struct regmap *cfg;

	struct clk *free_ck;



	struct list_head ports;
@@ -646,7 +650,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 
		return err;

	}



	if (of_find_property(dev->of_node, "interrupt-names", NULL))

		port->irq = platform_get_irq_byname(pdev, "pcie_irq");

	else

		port->irq = platform_get_irq(pdev, port->slot);



	if (port->irq < 0)

		return port->irq;
@@ -678,6 +686,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
		val |= PCIE_CSR_LTSSM_EN(port->slot) |

		       PCIE_CSR_ASPM_L1_EN(port->slot);

		writel(val, pcie->base + PCIE_SYS_CFG_V2);

	} else if (pcie->cfg) {

		val = PCIE_CSR_LTSSM_EN(port->slot) |

		      PCIE_CSR_ASPM_L1_EN(port->slot);

		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);

	}



	/* Assert all reset signals */
@@ -981,6 +993,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 
	struct device *dev = pcie->dev;

	struct platform_device *pdev = to_platform_device(dev);

	struct resource *regs;

	struct device_node *cfg_node;

	int err;



	/* get shared registers, which are optional */
@@ -991,6 +1004,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 
			return PTR_ERR(pcie->base);

	}



	cfg_node = of_find_compatible_node(NULL, NULL,

					   "mediatek,generic-pciecfg");

	if (cfg_node) {

		pcie->cfg = syscon_node_to_regmap(cfg_node);

		if (IS_ERR(pcie->cfg))

			return PTR_ERR(pcie->cfg);

	}



	pcie->free_ck = devm_clk_get(dev, "free_ck");

	if (IS_ERR(pcie->free_ck)) {

		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
@@ -1023,14 +1044,14 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) 
	struct device *dev = pcie->dev;

	struct device_node *node = dev->of_node, *child;

	struct mtk_pcie_port *port, *tmp;

	int err;

	int err, slot;



	slot = of_get_pci_domain_nr(dev->of_node);

	if (slot < 0) {

		for_each_available_child_of_node(node, child) {

		int slot;



			err = of_pci_get_devfn(child);

			if (err < 0) {

			dev_err(dev, "failed to parse devfn: %d\n", err);

				dev_err(dev, "failed to get devfn: %d\n", err);

				goto error_put_node;

			}
@@ -1040,6 +1061,11 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) 
			if (err)

				goto error_put_node;

		}

	} else {

		err = mtk_pcie_parse_port(pcie, node, slot);

		if (err)

			return err;

	}



	err = mtk_pcie_subsys_powerup(pcie);

	if (err)