Commit af42a0d4 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/keembay' 

- Add Intel Keem Bay PCIe controller driver and DT binding (Srikanth
  Thokala)

* remotes/lorenzo/pci/keembay:
  PCI: keembay: Add support for Intel Keem Bay
  dt-bindings: PCI: Add Intel Keem Bay PCIe controller
parents c1bb1449 0c87f90b

Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel Keem Bay PCIe controller Endpoint mode



maintainers:

  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

  - Srikanth Thokala <srikanth.thokala@intel.com>



properties:

  compatible:

    const: intel,keembay-pcie-ep



  reg:

    maxItems: 5



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: addr_space

      - const: apb



  interrupts:

    maxItems: 4



  interrupt-names:

    items:

      - const: pcie

      - const: pcie_ev

      - const: pcie_err

      - const: pcie_mem_access



  num-lanes:

    description: Number of lanes to use.

    enum: [ 1, 2 ]



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    pcie-ep@37000000 {

          compatible = "intel,keembay-pcie-ep";

          reg = <0x37000000 0x00001000>,

                <0x37100000 0x00001000>,

                <0x37300000 0x00001000>,

                <0x36000000 0x01000000>,

                <0x37800000 0x00000200>;

          reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";

          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

                       <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,

                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

                       <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

          interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";

          num-lanes = <2>;

    };

Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel Keem Bay PCIe controller Root Complex mode



maintainers:

  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

  - Srikanth Thokala <srikanth.thokala@intel.com>



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: intel,keembay-pcie



  ranges:

    maxItems: 1



  reset-gpios:

    maxItems: 1



  reg:

    maxItems: 4



  reg-names:

    items:

      - const: dbi

      - const: atu

      - const: config

      - const: apb



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: master

      - const: aux



  interrupts:

    maxItems: 3



  interrupt-names:

    items:

      - const: pcie

      - const: pcie_ev

      - const: pcie_err



  num-lanes:

    description: Number of lanes to use.

    enum: [ 1, 2 ]



required:

  - compatible

  - reg

  - reg-names

  - ranges

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - reset-gpios



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/gpio/gpio.h>

    #define KEEM_BAY_A53_PCIE

    #define KEEM_BAY_A53_AUX_PCIE

    pcie@37000000 {

          compatible = "intel,keembay-pcie";

          reg = <0x37000000 0x00001000>,

                <0x37300000 0x00001000>,

                <0x36e00000 0x00200000>,

                <0x37800000 0x00000200>;

          reg-names = "dbi", "atu", "config", "apb";

          #address-cells = <3>;

          #size-cells = <2>;

          device_type = "pci";

          ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;

          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

                       <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;

          interrupt-names = "pcie", "pcie_ev", "pcie_err";

          clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,

                   <&scmi_clk KEEM_BAY_A53_AUX_PCIE>;

          clock-names = "master", "aux";

          reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;

          num-lanes = <2>;

    };

MAINTAINERS

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@@ -14424,6 +14424,13 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt

F:	drivers/pci/controller/dwc/pcie-histb.c









PCIE DRIVER FOR INTEL KEEM BAY









M:	Srikanth Thokala <srikanth.thokala@intel.com>









L:	linux-pci@vger.kernel.org









S:	Supported









F:	Documentation/devicetree/bindings/pci/intel,keembay-pcie*









F:	drivers/pci/controller/dwc/pcie-keembay.c

















PCIE DRIVER FOR MEDIATEK









M:	Ryder Lee <ryder.lee@mediatek.com>









M:	Jianjun Wang <jianjun.wang@mediatek.com>
































drivers/pci/controller/dwc/Kconfig



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@@ -236,6 +236,34 @@ config PCIE_INTEL_GW







	  The PCIe controller uses the DesignWare core plus Intel-specific









	  hardware wrappers.



















config PCIE_KEEMBAY









	bool



















config PCIE_KEEMBAY_HOST









	bool "Intel Keem Bay PCIe controller - Host mode"









	depends on ARCH_KEEMBAY || COMPILE_TEST









	depends on PCI && PCI_MSI_IRQ_DOMAIN









	select PCIE_DW_HOST









	select PCIE_KEEMBAY









	help









	  Say 'Y' here to enable support for the PCIe controller in Keem Bay









	  to work in host mode.









	  The PCIe controller is based on DesignWare Hardware and uses









	  DesignWare core functions.



















config PCIE_KEEMBAY_EP









	bool "Intel Keem Bay PCIe controller - Endpoint mode"









	depends on ARCH_KEEMBAY || COMPILE_TEST









	depends on PCI && PCI_MSI_IRQ_DOMAIN









	depends on PCI_ENDPOINT









	select PCIE_DW_EP









	select PCIE_KEEMBAY









	help









	  Say 'Y' here to enable support for the PCIe controller in Keem Bay









	  to work in endpoint mode.









	  The PCIe controller is based on DesignWare Hardware and uses









	  DesignWare core functions.



















config PCIE_KIRIN









	depends on OF && (ARM64 || COMPILE_TEST)









	bool "HiSilicon Kirin series SoCs PCIe controllers"
































drivers/pci/controller/dwc/Makefile



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@@ -16,6 +16,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o







obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o









obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o









obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o









obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o









obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o









obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o









obj-$(CONFIG_PCI_MESON) += pci-meson.o