Commit c4e181d6 authored by Anson Huang's avatar Anson Huang Committed by Philipp Zabel
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dt-bindings: reset: imx7: Document usage on i.MX8MP SoC 



The driver now supports i.MX8MP, so update bindings accordingly.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent ecd910f4

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

+3 −1
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required properties: 
	- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"

	- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"

	- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"

	- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt
@@ -51,4 +52,5 @@ For list of all valid reset indices see 
<dt-bindings/reset/imx7-reset.h> for i.MX7,

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN
 
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and

<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP

include/dt-bindings/reset/imx8mp-reset.h

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+50 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright 2020 NXP

 */



#ifndef DT_BINDING_RESET_IMX8MP_H

#define DT_BINDING_RESET_IMX8MP_H



#define IMX8MP_RESET_A53_CORE_POR_RESET0	0

#define IMX8MP_RESET_A53_CORE_POR_RESET1	1

#define IMX8MP_RESET_A53_CORE_POR_RESET2	2

#define IMX8MP_RESET_A53_CORE_POR_RESET3	3

#define IMX8MP_RESET_A53_CORE_RESET0		4

#define IMX8MP_RESET_A53_CORE_RESET1		5

#define IMX8MP_RESET_A53_CORE_RESET2		6

#define IMX8MP_RESET_A53_CORE_RESET3		7

#define IMX8MP_RESET_A53_DBG_RESET0		8

#define IMX8MP_RESET_A53_DBG_RESET1		9

#define IMX8MP_RESET_A53_DBG_RESET2		10

#define IMX8MP_RESET_A53_DBG_RESET3		11

#define IMX8MP_RESET_A53_ETM_RESET0		12

#define IMX8MP_RESET_A53_ETM_RESET1		13

#define IMX8MP_RESET_A53_ETM_RESET2		14

#define IMX8MP_RESET_A53_ETM_RESET3		15

#define IMX8MP_RESET_A53_SOC_DBG_RESET		16

#define IMX8MP_RESET_A53_L2RESET		17

#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST	18

#define IMX8MP_RESET_OTG1_PHY_RESET		19

#define IMX8MP_RESET_OTG2_PHY_RESET		20

#define IMX8MP_RESET_SUPERMIX_RESET		21

#define IMX8MP_RESET_AUDIOMIX_RESET		22

#define IMX8MP_RESET_MLMIX_RESET		23

#define IMX8MP_RESET_PCIEPHY			24

#define IMX8MP_RESET_PCIEPHY_PERST		25

#define IMX8MP_RESET_PCIE_CTRL_APPS_EN		26

#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF	27

#define IMX8MP_RESET_HDMI_PHY_APB_RESET		28

#define IMX8MP_RESET_MEDIA_RESET		29

#define IMX8MP_RESET_GPU2D_RESET		30

#define IMX8MP_RESET_GPU3D_RESET		31

#define IMX8MP_RESET_GPU_RESET			32

#define IMX8MP_RESET_VPU_RESET			33

#define IMX8MP_RESET_VPU_G1_RESET		34

#define IMX8MP_RESET_VPU_G2_RESET		35

#define IMX8MP_RESET_VPUVC8KE_RESET		36

#define IMX8MP_RESET_NOC_RESET			37



#define IMX8MP_RESET_NUM			38



#endif