Commit ecd910f4 authored by Anson Huang's avatar Anson Huang Committed by Philipp Zabel
Browse files

dt-bindings: reset: imx7: Add support for i.MX8MN 



i.MX8MN can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MN.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 3a5fc252

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

+3 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
	- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"

	- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"

	- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"

	- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt
@@ -49,4 +50,5 @@ Example: 
For list of all valid reset indices see

<dt-bindings/reset/imx7-reset.h> for i.MX7,

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM
 
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN

include/dt-bindings/reset/imx8mq-reset.h

+28 −28
Original line number Diff line number Diff line
@@ -28,36 +28,36 @@ 
#define IMX8MQ_RESET_A53_L2RESET		17

#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST	18

#define IMX8MQ_RESET_OTG1_PHY_RESET		19

#define IMX8MQ_RESET_OTG2_PHY_RESET		20

#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N	21

#define IMX8MQ_RESET_MIPI_DSI_RESET_N		22

#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N	23

#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N	24

#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N	25

#define IMX8MQ_RESET_PCIEPHY			26

#define IMX8MQ_RESET_PCIEPHY_PERST		27

#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN		28

#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF	29

#define IMX8MQ_RESET_HDMI_PHY_APB_RESET		30	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_OTG2_PHY_RESET		20	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N	21	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_DSI_RESET_N		22	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N	23	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N	24	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N	25	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIEPHY			26	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIEPHY_PERST		27	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN		28	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF	29	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_HDMI_PHY_APB_RESET		30	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_DISP_RESET			31

#define IMX8MQ_RESET_GPU_RESET			32

#define IMX8MQ_RESET_VPU_RESET			33

#define IMX8MQ_RESET_PCIEPHY2			34	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_PCIEPHY2_PERST		35	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN		36	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF	37	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET	38	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET	39	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET	40	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET	41	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET	42	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET	43	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_DDRC1_PRST			44

#define IMX8MQ_RESET_DDRC1_CORE_RESET		45

#define IMX8MQ_RESET_DDRC1_PHY_RESET		46

#define IMX8MQ_RESET_DDRC2_PRST			47	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_DDRC2_CORE_RESET		48	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_DDRC2_PHY_RESET		49	/* i.MX8MM does NOT support */

#define IMX8MQ_RESET_VPU_RESET			33	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIEPHY2			34	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIEPHY2_PERST		35	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN		36	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF	37	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET	38	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET	39	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET	40	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET	41	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET	42	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET	43	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC1_PRST			44	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC1_CORE_RESET		45	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC1_PHY_RESET		46	/* i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC2_PRST			47	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC2_CORE_RESET		48	/* i.MX8MM/i.MX8MN does NOT support */

#define IMX8MQ_RESET_DDRC2_PHY_RESET		49	/* i.MX8MM/i.MX8MN does NOT support */



#define IMX8MQ_RESET_NUM			50