Unverified Commit c45fc916 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
Browse files

riscv: enable software resend of irqs 

The PLIC specification does not describe the interrupt pendings bits as
read-write, only that they "can be read". To allow for retriggering of
interrupts (and the use of the irq debugfs interface) enable
HARDIRQS_SW_RESEND for RISC-V.

Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits


Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU
Reviewed-by: default avatarBjörn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/r/20220729111116.259146-1-conor.dooley@microchip.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 5a5294fb

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ config RISCV 
	select GENERIC_SMP_IDLE_THREAD

	select GENERIC_TIME_VSYSCALL if MMU && 64BIT

	select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO

	select HARDIRQS_SW_RESEND

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL

	select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL