Unverified Commit 5a5294fb authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Re-enable counter access from userspace 

These counters were part of the ISA when we froze the uABI, removing
them breaks userspace.

Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/


Fixes: e9991434 ("RISC-V: Add perf platform driver based on SBI PMU extension")
Tested-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220928131807.30386-1-palmer@rivosinc.com


Cc: stable@vger.kernel.org
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent a8616d2d

drivers/perf/riscv_pmu_sbi.c

+5 −2
Original line number Diff line number Diff line
@@ -652,8 +652,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) 
	struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);

	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);



	/* Enable the access for TIME csr only from the user mode now */

	csr_write(CSR_SCOUNTEREN, 0x2);

	/*

	 * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,

	 * as is necessary to maintain uABI compatibility.

	 */

	csr_write(CSR_SCOUNTEREN, 0x7);



	/* Stop all the counters so that they can be enabled from perf */

	pmu_sbi_stop_all(pmu);