Commit c40e6c67 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
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drm/msm/dpu: handle merge_3d configuration in hw_ctl block 



Active HW CTL blocks need separate handling for merge_3d flushes.
Implement necessary merge_3d configuration and flushing.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 4369c93c

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+16 −0
Original line number Diff line number Diff line
@@ -22,7 +22,9 @@ 
#define   CTL_PREPARE                   0x0d0

#define   CTL_SW_RESET                  0x030

#define   CTL_LAYER_EXTN_OFFSET         0x40

#define   CTL_MERGE_3D_ACTIVE           0x0E4

#define   CTL_INTF_ACTIVE               0x0F4

#define   CTL_MERGE_3D_FLUSH            0x100

#define   CTL_INTF_FLUSH                0x110

#define   CTL_INTF_MASTER               0x134
@@ -30,6 +32,7 @@ 
#define CTL_FLUSH_MASK_CTL              BIT(17)



#define DPU_REG_RESET_TIMEOUT_US        2000

#define  MERGE_3D_IDX   23

#define  INTF_IDX       31



static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
@@ -112,6 +115,9 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) 
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)

{



	if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,

				ctx->pending_merge_3d_flush_mask);

	if (ctx->pending_flush_mask & BIT(INTF_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,

				ctx->pending_intf_flush_mask);
@@ -242,6 +248,13 @@ static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, 
	ctx->pending_flush_mask |= BIT(INTF_IDX);

}



static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,

		enum dpu_merge_3d merge_3d)

{

	ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0);

	ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);

}



static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct dpu_hw_ctl *ctx,

	enum dpu_dspp dspp)

{
@@ -483,6 +496,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 


	DPU_REG_WRITE(c, CTL_TOP, mode_sel);

	DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);

	DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0));

}



static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
@@ -523,6 +537,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, 
		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;

		ops->update_pending_flush_intf =

			dpu_hw_ctl_update_pending_flush_intf_v1;

		ops->update_pending_flush_merge_3d =

			dpu_hw_ctl_update_pending_flush_merge_3d_v1;

	} else {

		ops->trigger_flush = dpu_hw_ctl_trigger_flush;

		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

+12 −0
Original line number Diff line number Diff line
@@ -37,12 +37,14 @@ struct dpu_hw_stage_cfg { 
 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface

 * @intf :                 Interface id

 * @mode_3d:               3d mux configuration

 * @merge_3d:              3d merge block used

 * @intf_mode_sel:         Interface mode, cmd / vid

 * @stream_sel:            Stream selection for multi-stream interfaces

 */

struct dpu_hw_intf_cfg {

	enum dpu_intf intf;

	enum dpu_3d_blend_mode mode_3d;

	enum dpu_merge_3d merge_3d;

	enum dpu_ctl_mode_sel intf_mode_sel;

	int stream_sel;

};
@@ -99,6 +101,15 @@ struct dpu_hw_ctl_ops { 
	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,

		enum dpu_intf blk);



	/**

	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask

	 * No effect on hardware

	 * @ctx       : ctl path ctx pointer

	 * @blk       : interface block index

	 */

	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,

		enum dpu_merge_3d blk);



	/**

	 * Write the value of the pending_flush_mask to hardware

	 * @ctx       : ctl path ctx pointer
@@ -181,6 +192,7 @@ struct dpu_hw_ctl { 
	const struct dpu_lm_cfg *mixer_hw_caps;

	u32 pending_flush_mask;

	u32 pending_intf_flush_mask;

	u32 pending_merge_3d_flush_mask;



	/* ops */

	struct dpu_hw_ctl_ops ops;