dt-bindings: pinctrl: convert rockchip,pinctrl.txt to YAML

* Rockchip Pinmux Controller

The Rockchip Pinmux Controller, enables the IC

to share one PAD to several functional blocks. The sharing is done by

multiplexing the PAD input/output signals. For each PAD there are several

muxing options with option 0 being the use as a GPIO.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The Rockchip pin configuration node is a node of a group of pins which can be

used for a specific device or function. This node represents both mux and

config of the pins in that group. The 'pins' selects the function mode(also

named pin mode) this pin can work on and the 'config' configures various pad

settings such as pull-up, etc.

The pins are grouped into up to 5 individual pin banks which need to be

defined as gpio sub-nodes of the pinmux controller.

Required properties for iomux controller:

  - compatible: should be

		"rockchip,px30-pinctrl":    for Rockchip PX30

		"rockchip,rv1108-pinctrl":  for Rockchip RV1108

		"rockchip,rk2928-pinctrl":  for Rockchip RK2928

		"rockchip,rk3066a-pinctrl": for Rockchip RK3066a

		"rockchip,rk3066b-pinctrl": for Rockchip RK3066b

		"rockchip,rk3128-pinctrl":  for Rockchip RK3128

		"rockchip,rk3188-pinctrl":  for Rockchip RK3188

		"rockchip,rk3228-pinctrl":  for Rockchip RK3228

		"rockchip,rk3288-pinctrl":  for Rockchip RK3288

		"rockchip,rk3308-pinctrl":  for Rockchip RK3308

		"rockchip,rk3328-pinctrl":  for Rockchip RK3328

		"rockchip,rk3368-pinctrl":  for Rockchip RK3368

		"rockchip,rk3399-pinctrl":  for Rockchip RK3399

		"rockchip,rk3568-pinctrl":  for Rockchip RK3568

  - rockchip,grf: phandle referencing a syscon providing the

	 "general register files"

Optional properties for iomux controller:

  - rockchip,pmu: phandle referencing a syscon providing the pmu registers

	 as some SoCs carry parts of the iomux controller registers there.

	 Required for at least rk3188 and rk3288. On the rk3368 this should

	 point to the PMUGRF syscon.

Deprecated properties for iomux controller:

  - reg: first element is the general register space of the iomux controller

	 It should be large enough to contain also separate pull registers.

	 second element is the separate pull register space of the rk3188.

	 Use rockchip,grf and rockchip,pmu described above instead.

Required properties for gpio sub nodes:

See rockchip,gpio-bank.yaml

Required properties for pin configuration node:

  - rockchip,pins: 3 integers array, represents a group of pins mux and config

    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.

    The MUX 0 means gpio and MUX 1 to N mean the specific device function.

    The phandle of a node containing the generic pinconfig options

    to use, as described in pinctrl-bindings.txt in this directory.

Examples:

#include <dt-bindings/pinctrl/rockchip.h>

...

pinctrl@20008000 {

	compatible = "rockchip,rk3066a-pinctrl";

	rockchip,grf = <&grf>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	gpio0: gpio0@20034000 {

		compatible = "rockchip,gpio-bank";

		reg = <0x20034000 0x100>;

		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clk_gates8 9>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

	...

	pcfg_pull_default: pcfg_pull_default {

		bias-pull-pin-default

	};

	uart2 {

		uart2_xfer: uart2-xfer {

			rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,

					<1 RK_PB1 1 &pcfg_pull_default>;

		};

	};

};

uart2: serial@20064000 {

	compatible = "snps,dw-apb-uart";

	reg = <0x20064000 0x400>;

	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

	reg-shift = <2>;

	reg-io-width = <1>;

	clocks = <&mux_uart2>;

	pinctrl-names = "default";

	pinctrl-0 = <&uart2_xfer>;

};

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Pinmux Controller

maintainers:

  - Heiko Stuebner <heiko@sntech.de>

description: |

  The Rockchip Pinmux Controller enables the IC to share one PAD

  to several functional blocks. The sharing is done by multiplexing

  the PAD input/output signals. For each PAD there are several muxing

  options with option 0 being used as a GPIO.

  Please refer to pinctrl-bindings.txt in this directory for details of the

  common pinctrl bindings used by client devices, including the meaning of the

  phrase "pin configuration node".

  The Rockchip pin configuration node is a node of a group of pins which can be

  used for a specific device or function. This node represents both mux and

  config of the pins in that group. The 'pins' selects the function mode

  (also named pin mode) this pin can work on and the 'config' configures

  various pad settings such as pull-up, etc.

  The pins are grouped into up to 9 individual pin banks which need to be

  defined as gpio sub-nodes of the pinmux controller.

properties:

  compatible:

    enum:

      - rockchip,px30-pinctrl

      - rockchip,rk2928-pinctrl

      - rockchip,rk3066a-pinctrl

      - rockchip,rk3066b-pinctrl

      - rockchip,rk3128-pinctrl

      - rockchip,rk3188-pinctrl

      - rockchip,rk3228-pinctrl

      - rockchip,rk3288-pinctrl

      - rockchip,rk3308-pinctrl

      - rockchip,rk3328-pinctrl

      - rockchip,rk3368-pinctrl

      - rockchip,rk3399-pinctrl

      - rockchip,rk3568-pinctrl

      - rockchip,rv1108-pinctrl

  rockchip,grf:

    $ref: "/schemas/types.yaml#/definitions/phandle"

    description:

      The phandle of the syscon node for the GRF registers.

  rockchip,pmu:

    $ref: "/schemas/types.yaml#/definitions/phandle"

    description:

      The phandle of the syscon node for the PMU registers,

      as some SoCs carry parts of the iomux controller registers there.

      Required for at least rk3188 and rk3288. On the rk3368 this should

      point to the PMUGRF syscon.

  "#address-cells":

    enum: [1, 2]

  "#size-cells":

    enum: [1, 2]

  ranges: true

required:

  - compatible

  - rockchip,grf

  - "#address-cells"

  - "#size-cells"

  - ranges

patternProperties:

  "gpio@[0-9a-f]+$":

    type: object

    $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"

    unevaluatedProperties: false

  "pcfg-[a-z0-9-]+$":

    type: object

    properties:

      bias-disable: true

      bias-pull-down: true

      bias-pull-pin-default: true

      bias-pull-up: true

      drive-strength:

        minimum: 0

        maximum: 20

      input-enable: true

      input-schmitt-enable: true

      output-high: true

      output-low: true

    additionalProperties: false

additionalProperties:

  type: object

  additionalProperties:

    type: object

    properties:

      rockchip,pins:

        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"

        minItems: 1

        items:

          items:

            - minimum: 0

              maximum: 8

              description:

                Pin bank.

            - minimum: 0

              maximum: 31

              description:

                Pin bank index.

            - minimum: 0

              maximum: 6

              description:

                Mux 0 means GPIO and mux 1 to N means

                the specific device function.

            - description:

                The phandle of a node contains the generic pinconfig options

                to use as described in pinctrl-bindings.txt.

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/pinctrl/rockchip.h>

    pinctrl: pinctrl {

      compatible = "rockchip,rk3066a-pinctrl";

      rockchip,grf = <&grf>;

      #address-cells = <1>;

      #size-cells = <1>;

      ranges;

      gpio0: gpio@20034000 {

        compatible = "rockchip,gpio-bank";

        reg = <0x20034000 0x100>;

        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk_gates8 9>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

      };

      pcfg_pull_default: pcfg-pull-default {

        bias-pull-pin-default;

      };

      uart2 {

        uart2_xfer: uart2-xfer {

          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,

                          <1 RK_PB1 1 &pcfg_pull_default>;

        };

      };

    };

    uart2: serial@20064000 {

      compatible = "snps,dw-apb-uart";

      reg = <0x20064000 0x400>;

      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&mux_uart2>;

      pinctrl-0 = <&uart2_xfer>;

      pinctrl-names = "default";

      reg-io-width = <1>;

      reg-shift = <2>;

    };