Commit c3b8e079 authored by Ilya Lipnitskiy's avatar Ilya Lipnitskiy Committed by David S. Miller
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net: dsa: mt7530: setup core clock even in TRGMII mode 



A recent change to MIPS ralink reset logic made it so mt7530 actually
resets the switch on platforms such as mt7621 (where bit 2 is the reset
line for the switch). That exposed an issue where the switch would not
function properly in TRGMII mode after a reset.

Reconfigure core clock in TRGMII mode to fix the issue.

Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.

Fixes: 3f9ef778 ("MIPS: ralink: manage low reset lines")
Signed-off-by: default avatarIlya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2e5de7e0

drivers/net/dsa/mt7530.c

+25 −27
Original line number Diff line number Diff line
@@ -436,7 +436,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 
			     TD_DM_DRVP(8) | TD_DM_DRVN(8));



	/* Setup core clock for MT7530 */

	if (!trgint) {

	/* Disable MT7530 core clock */

	core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
@@ -463,7 +462,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 


	/* Enable MT7530 core clock */

	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);

	}



	/* Setup the MT7530 TRGMII Tx Clock */

	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);