Unverified Commit c35f3aa3 authored by Andy Chiu's avatar Andy Chiu Committed by Palmer Dabbelt
Browse files

RISC-V: vector: export VLENB csr in __sc_riscv_v_state 



VLENB is critical for callers of ptrace to reconstruct Vector register
files from the register dump of NT_RISCV_VECTOR. Also, future systems
may will have a writable VLENB, so add it now to potentially save future
compatibility issue.

Fixes: 0c59922c ("riscv: Add ptrace vector support")
Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20230816155450.26200-3-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent e3f9324b

arch/riscv/include/asm/vector.h

+2 −1
Original line number Diff line number Diff line
@@ -70,8 +70,9 @@ static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest) 
		"csrr	%1, " __stringify(CSR_VTYPE) "\n\t"

		"csrr	%2, " __stringify(CSR_VL) "\n\t"

		"csrr	%3, " __stringify(CSR_VCSR) "\n\t"

		"csrr	%4, " __stringify(CSR_VLENB) "\n\t"

		: "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest->vl),

		  "=r" (dest->vcsr) : :);

		  "=r" (dest->vcsr), "=r" (dest->vlenb) : :);

}



static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src)

arch/riscv/include/uapi/asm/ptrace.h

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ struct __riscv_v_ext_state { 
	unsigned long vl;

	unsigned long vtype;

	unsigned long vcsr;

	unsigned long vlenb;

	void *datap;

	/*

	 * In signal handler, datap will be set a correct user stack offset