Unverified Commit e3f9324b authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Remove ptrace support for vectors 



We've found two bugs here: NT_RISCV_VECTOR steps on NT_RISCV_CSR (which
is only for embedded), and we don't have vlenb in the core dumps.  Given
that we've have a pair of bugs croup up as part of the GDB review we've
probably got other issues, so let's just cut this for 6.5 and get it
right.

Fixes: 0c59922c ("riscv: Add ptrace vector support")
Reviewed-by: default avatarMaciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20230816155450.26200-2-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 06c2afb8

arch/riscv/kernel/ptrace.c

+0 −69
Original line number Diff line number Diff line
@@ -25,9 +25,6 @@ enum riscv_regset { 
#ifdef CONFIG_FPU

	REGSET_F,

#endif

#ifdef CONFIG_RISCV_ISA_V

	REGSET_V,

#endif

};



static int riscv_gpr_get(struct task_struct *target,
@@ -84,61 +81,6 @@ static int riscv_fpr_set(struct task_struct *target, 
}

#endif



#ifdef CONFIG_RISCV_ISA_V

static int riscv_vr_get(struct task_struct *target,

			const struct user_regset *regset,

			struct membuf to)

{

	struct __riscv_v_ext_state *vstate = &target->thread.vstate;



	if (!riscv_v_vstate_query(task_pt_regs(target)))

		return -EINVAL;



	/*

	 * Ensure the vector registers have been saved to the memory before

	 * copying them to membuf.

	 */

	if (target == current)

		riscv_v_vstate_save(current, task_pt_regs(current));



	/* Copy vector header from vstate. */

	membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap));

	membuf_zero(&to, sizeof(vstate->datap));



	/* Copy all the vector registers from vstate. */

	return membuf_write(&to, vstate->datap, riscv_v_vsize);

}



static int riscv_vr_set(struct task_struct *target,

			const struct user_regset *regset,

			unsigned int pos, unsigned int count,

			const void *kbuf, const void __user *ubuf)

{

	int ret, size;

	struct __riscv_v_ext_state *vstate = &target->thread.vstate;



	if (!riscv_v_vstate_query(task_pt_regs(target)))

		return -EINVAL;



	/* Copy rest of the vstate except datap */

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,

				 offsetof(struct __riscv_v_ext_state, datap));

	if (unlikely(ret))

		return ret;



	/* Skip copy datap. */

	size = sizeof(vstate->datap);

	count -= size;

	ubuf += size;



	/* Copy all the vector registers. */

	pos = 0;

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,

				 0, riscv_v_vsize);

	return ret;

}

#endif



static const struct user_regset riscv_user_regset[] = {

	[REGSET_X] = {

		.core_note_type = NT_PRSTATUS,
@@ -158,17 +100,6 @@ static const struct user_regset riscv_user_regset[] = { 
		.set = riscv_fpr_set,

	},

#endif

#ifdef CONFIG_RISCV_ISA_V

	[REGSET_V] = {

		.core_note_type = NT_RISCV_VECTOR,

		.align = 16,

		.n = ((32 * RISCV_MAX_VLENB) +

		      sizeof(struct __riscv_v_ext_state)) / sizeof(__u32),

		.size = sizeof(__u32),

		.regset_get = riscv_vr_get,

		.set = riscv_vr_set,

	},

#endif

};



static const struct user_regset_view riscv_user_native_view = {

include/uapi/linux/elf.h

+0 −1
Original line number Diff line number Diff line
@@ -443,7 +443,6 @@ typedef struct elf64_shdr { 
#define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */

#define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */

#define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */

#define NT_RISCV_VECTOR	0x900		/* RISC-V vector registers */

#define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers */

#define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and status registers */

#define NT_LOONGARCH_LSX	0xa02	/* LoongArch Loongson SIMD Extension registers */